Patents by Inventor Wayne A. Perzan

Wayne A. Perzan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4979104
    Abstract: A microprocessor control system for use in an asynchronous data communication system and comprising a receive microprocessor and a transmit microprocessor along with a paged memory for storing channel line tables. Separate receive and transmit channel number registers control access to the paged memory. Control means is provided preferably in the form of a programmable memory for controlling the sequenching of channel numbers whereby one microprocessor is adapted to access channels in an incrementing manner while the other accesses in decrementing manner. When one microprocessor gains access to a specific line table excludes the other microprocessor from accessing that line table until the first microprocessor suspends off of that line table.
    Type: Grant
    Filed: March 31, 1987
    Date of Patent: December 18, 1990
    Assignee: Bull HN Information Systems Inc.
    Inventors: Thomas O. Holtey, Thomas L. Murray, Jr., Wayne A. Perzan, Scott W. Smith
  • Patent number: 4965721
    Abstract: A firmware state apparatus for controlling data transfer on multiple independent data lines between a telephone communications system and computer system. At least one processor having a program counter is employed for control data transfer. A processor memory is associated with the processor and has a plurality of firmware instructions divided into groups based upon the number of predefined states which are required for performing data transfer. Certain groups of instructions include test instructions for evaluating conditions related to the line to control sequencing to a next one of the predefined states. A shared memory has a plurality of locations for line table information for at least one line with at least one location containing a program counter address specifying a starting instruction of a corresponding one of the group of instructions to be executed by the processor.
    Type: Grant
    Filed: March 31, 1987
    Date of Patent: October 23, 1990
    Assignee: Bull HN Information Systems Inc.
    Inventors: Thomas O. Holtey, Thomas L. Murray, Jr., Wayne A. Perzan, Scott W. Smith
  • Patent number: 4945473
    Abstract: A communications controller interface for emulating the previous system employing a plurality of line units in which data is transmitted and received. The interface includes a microprocessor-controlled interface control unit having an interface memory having a plurality of addressable storage locations. The interface memory is mapped by dividing it into a number of groups of locations corresponding to the number of communication lines with each group of locations being subdivided into further locations including a location for storage of receive data, a location for storage of transmit data, and a control location. There are a number of control elements each for generating a sequence of signals for different tasks to be performed by the interface control unit.
    Type: Grant
    Filed: May 15, 1987
    Date of Patent: July 31, 1990
    Assignee: Bull HN Information Systems Inc.
    Inventors: Thomas O. Holtey, Thomas L. Murray, Jr., Scott W. Smith, Wayne A. Perzan