Abstract: A particular voltage level in an integrated MOS chip is maintained by defining that level as an integral multiple of drain-to-gate voltage thresholds and by actively controlling that level in response to deviations therefrom. Plural MOSFET elements are connected in circuit so that their drain-to-gate capacitances are serially effective across internal signal lines (e.g. busses) for bias so as to establish a reference level to be compared with the actual voltage on these signal lines; and through feedback the signal level as applied from outside of the chip to these lines or busses is reduced to obtain the desired multiple threshold voltage as operating voltage on these lines for use by other elements in the chip.