Abstract: A semiconductor device includes a primary memory array, primary addressing circuitry, a redundant memory array, redundant addressing circuitry, and a first signal pad. The primary memory array includes primary memory elements operable to store data, and the primary addressing circuit is operable to select the primary memory elements. The redundant memory array includes redundant memory elements operable to store data and is also operable to be programmed from a programmable state to provide redundant memory elements for defective primary memory elements. The first signal pad is operable to receive serial selection data, and the redundant addressing circuit is connected to the first signal pad and is operable to receive the serial selection data from the first signal pad and select the redundant memory elements in response.

Abstract: A semiconductor device includes a first power pad, a second power pad, a first adjacent bus pair, and a second adjacent bus pair. The first power pad is operable to supply a first potential, and the second power pad operable to supply a second potential. The first adjacent bus pair is disposed on a first layer of the semiconductor device and connected to the first and second power pad. The second adjacent bus pair is disposed on the second layer of the semiconductor device and is connected to the first and second power pads, and is also underlying the first adjacent bus pair.

Abstract: A semiconductor device a first power pad, a second power pad, a first power network, and a second power network. The first power pad is operable to supply a first potential, and the second power pad is operable to supply a second potential. The first power network defines a first periphery in the semiconductor device and is coupled to the first power pad and the second power pad. The second power network defines a second periphery in the semiconductor device and is coupled to the first power pad and the second power pad.

Abstract: A semiconductor device comprises a first power pad, a second power pad, a first power network, and a second power network. The first power pad is operable to supply a first potential, and the second power pad is operable to supply a second potential. The first power network defines a first periphery in the semiconductor device and is coupled to the first power pad and the second power pad. The second power network defines a second periphery in the semiconductor device and is coupled to the first power pad and the second power pad.

Abstract: A semiconductor device includes a primary memory array, primary addressing circuitry, a redundant memory array, redundant addressing circuitry, and a first signal pad. The primary memory array includes primary memory elements operable to store data, and the primary addressing circuit is operable to select the primary memory elements. The redundant memory array includes redundant memory elements operable to store data and is also operable to be programmed from a programmable state to provide redundant memory elements for defective primary memory elements. The first signal pad is operable to receive serial selection data, and the redundant addressing circuit is connected to the first signal pad and is operable to receive the serial selection data from the first signal pad and select the redundant memory elements in response.

Abstract: A semiconductor device includes a first power pad, a second power pad, a first adjacent bus pair, and a second adjacent bus pair. The first power pad is operable to supply a first potential, and the second power pad operable to supply a second potential. The first adjacent bus pair is disposed on a first layer of the semiconductor device and connected to the first and second power pad. The second adjacent bus pair is disposed on the second layer of the semiconductor device and is connected to the first and second power pads, and is also underlying the first adjacent bus pair.

Abstract: A magnetoresistive random access memory (MRAM) device includes a memory array having a plurality of bitlines and a plurality of wordlines intersecting the bitlines. A plurality of memory elements are located at the intersections of the wordlines and the bitlines and are operable to store data. A bitline selection circuit is operable to select a first bitline and to provide a first sense current to the first bitline to generate a first reference signal. A wordline selection circuit is operable to select wordlines and to provide wordline currents to a selected wordline after the first reference signal has stabilized and while the first sense current is applied to the first bitline.