Patents by Inventor Wayne Barrett

Wayne Barrett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12214559
    Abstract: According to the present invention, there is provided a pipe forming apparatus for forming a pipe at an installation site. The apparatus includes a former upon which material is wound, and a mold for receiving the former bearing the wound material. An applicator is provided for applying curable liquid within the mold. Advantageously, the pipe is formed at site to provide for efficient formation of a pipeline. A transported ISO container providing the material and curable liquid to the site can produce 800 metres of pipeline section, compared with 60 metres in the prior art, representing a significant increase in efficiency.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: February 4, 2025
    Assignee: NEXGEN PIPES PTE. LTD.
    Inventor: Wayne Barrett
  • Publication number: 20230085379
    Abstract: According to the present invention, there is provided a pipe forming apparatus for forming a pipe at an installation site. The apparatus includes a former upon which material is wound, and a mold for receiving the former bearing the wound material. An applicator is provided for applying curable liquid within the mold. Advantageously, the pipe is formed at site to provide for efficient formation of a pipeline. A transported ISO container providing the material and curable liquid to the site can produce 800 metres of pipeline section, compared with 60 metres in the prior art, representing a significant increase in efficiency.
    Type: Application
    Filed: July 31, 2020
    Publication date: March 16, 2023
    Inventor: Wayne BARRETT
  • Publication number: 20180186102
    Abstract: A pipe forming assembly and method of use is provided for forming a continuous length of pipe. In particular, the present invention concerns a pipe forming assembly including: a former; at least one applicator for applying material about the former, the at least one applicator being movable relative to the former while applying material to form the pipe; and a carriage for conveying the former and the at least one applicator along a surface for forming a continuous length of pipe.
    Type: Application
    Filed: June 27, 2016
    Publication date: July 5, 2018
    Inventor: Wayne BARRETT
  • Publication number: 20160146578
    Abstract: Polymeric compositions for use in preparing a ballistic material and ballistic materials capable of absorbing incoming projectiles prepared from the polymeric material are disclosed. The resulting ballistic materials are also disclosed. The materials have sufficient elasticity so that the polymer or polymer blend does not shatter when stuck with a high-velocity projectile. The polymer blends ideally have one or more of the following physical properties—a) a modulus of elasticity in the range of around 12,500 psi and around 19,000 psi, b) a max stress psi in the range of around 545 and around 985, and c) a tensile strength in the range of around 3.50 ft-lbf/in and around 11.00 ft-lbf/in. The thickness of the ballistic material is at least around 3 inches, with a size of around 4-5 inches square or diameter. Objects made of a hardened material, typically between about ¼ and ½ inch, can be interspersed throughout the interior volume of the material.
    Type: Application
    Filed: June 30, 2015
    Publication date: May 26, 2016
    Inventors: Leslie P. Duke, Wayne Barrett
  • Patent number: 7845266
    Abstract: A building block for constructing a projectile absorbing armor. The building block has at least one interlocking male connector and at least one female connector. The interlocking male connector and said female connector are sized for interlocking engagement. The invention is also generally directed to a structure having projectile absorbing armor having at least two building blocks in interlocking engagement. The building blocks are constructed from projectile resistant material and may have various features to prevent the passage of a projectile through the block.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: December 7, 2010
    Assignee: Ballistics Blocks LLC
    Inventors: Leslie P. Duke, Wayne Barrett
  • Publication number: 20100282060
    Abstract: A building block for constructing a projectile absorbing armor. The building block has at least one interlocking male connector and at least one female connector. The interlocking male connector and said female connector are sized for interlocking engagement. The invention is also generally directed to a structure having projectile absorbing armor having at least two building blocks in interlocking engagement. The building blocks are constructed from projectile resistant material and may have various features to prevent the passage of a projectile through the block.
    Type: Application
    Filed: January 8, 2007
    Publication date: November 11, 2010
    Inventors: Leslie P. Duke, Wayne Barrett
  • Patent number: 7761669
    Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brian David Allison, Wayne Barrett, Joseph Allen Kirscht, Elizabeth A. McGlone, Brian T. Vanderpool
  • Publication number: 20100173117
    Abstract: Polymeric compositions for use in preparing a ballistic material and ballistic materials capable of absorbing incoming projectiles prepared from the polymeric material are disclosed The resulting ballistic materials are also disclosed The materials have sufficient elasticity so that the polymer or polymer blend does not shatter when stuck with a high-velocity projectile The polymer blends ideally have one or more of the following physical properties—a) a modulus of elasticity in the range of around 12,500 psi and around 19,000-psi, b) a max stress psi in the range of around 545 and around 985, and c) a tensile strength in the range of around 3 50 ft-lbfl?n and around 11 OO ft-lbf/?n The thickness of the ballistic material is at least around 3 inches, with a size of around 4-5 inches square or diameter
    Type: Application
    Filed: January 8, 2008
    Publication date: July 8, 2010
    Inventors: Leslie P. Duke, Wayne Barrett
  • Publication number: 20090019239
    Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 15, 2009
    Inventors: Brian David Allison, Wayne Barrett, Joseph Allen Kirscht, Elizabeth A. McGlone, Brian T. Vanderpool
  • Publication number: 20090019238
    Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes fuller, requests are serviced in a manner that maximizes throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 15, 2009
    Inventors: Brian David Allison, Wayne Barrett, Joseph Allen Kirscht, Elizabeth A. McGlone, Brian T. Vanderpool
  • Publication number: 20080016484
    Abstract: A design structure includes a data communication circuit to facilitate communication between a deserializer, responsive to a serial data stream, which puts data onto a parallel bus, and a device that is in data communication therewith. The circuit a deserialization clock that asserts a clock read pulse each time data on the parallel bus is valid. A delay unit asserts a corresponding delayed clock pulse. The delayed clock pulse is delayed from the clock read pulse by a predetermined period. A clock tree repeats the delayed clock pulse and periodically asserts a plurality of end point repeated clock pulses, each of which has a substantially simultaneous leading edge. The predetermined amount of time is selected so as to cause each of the end point repeated clock signals to be asserted when data on the parallel bus is valid, thereby enabling the device to read data from the parallel bus.
    Type: Application
    Filed: September 25, 2007
    Publication date: January 17, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wayne Barrett, Todd Greenfield
  • Publication number: 20070255867
    Abstract: In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.
    Type: Application
    Filed: April 26, 2006
    Publication date: November 1, 2007
    Inventors: Wayne Barrett, Todd Greenfield
  • Publication number: 20070061519
    Abstract: An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data if the source has an exclusive copy of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 15, 2007
    Applicant: International Business Machines Corporation
    Inventors: Wayne Barrett, Kenneth Valk, Brian Vanderpool
  • Publication number: 20060248432
    Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 2, 2006
    Applicant: International Business Machines Corporation
    Inventors: Wayne Barrett, Philip Hillier, Joseph Kirscht, Elizabeth McGlone
  • Publication number: 20060143403
    Abstract: In a shared memory architecture, early coherency indication is used to notify a communications interface, prior to the data for a memory request is returned, and prior to updating a coherency directory in response to the memory request, that the return data can be used by the communications interface when it is received thereby from a source of the return data. By doing so, the communications interface can often begin forwarding the return data over its associated communication link with little or no latency once the data is retrieved from its source. In addition, the communications interface is often no longer required to wait for updating of the coherency directory to complete prior to forwarding the return data over the communication link. As such, the overall latency for handling the memory request is typically reduced.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 29, 2006
    Applicant: International Business Machines Corporation
    Inventors: Wayne Barrett, David Shedivy, Kenneth Valk, Brian Vanderpool
  • Publication number: 20060129726
    Abstract: In a first aspect, a first method is provided for processing commands on a bus. The first method includes the steps of (1) in a first phase of bus command processing, receiving a new command from a processor in a memory controller via the bus, wherein a command on the bus is processed in a plurality of sequential phases; (2) starting to perform memory controller tasks the results of which are required by a second phase of bus command processing; (3) before performing the second phase of bus command processing on the new command, determining whether there are any pending commands previously received in the memory controller that should complete before the second phase of processing is performed on the new command; and (4) if not, performing the second phase of processing on the new command without requiring the memory controller to insert a processing delay on the bus. Numerous other aspects are provided.
    Type: Application
    Filed: December 9, 2004
    Publication date: June 15, 2006
    Applicant: International Business Machines Corporation
    Inventors: Wayne Barrett, Brian Vanderpool
  • Publication number: 20060123206
    Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Inventors: Wayne Barrett, Brian Vanderpool