Abstract: A synchronous digital delay line that can be programmed by variable delay increments to independently delay the leading and trailing edges of a digital signal and that can be utilized to provide a wide range of digital delaying requirements. Bipolar input data is processed to develop a mark data pulse stream representing the leading edges of input data pulses and a space data pulse stream representing the trailing edges of input data pulses. Each data pulse stream is delayed separately by a programmable random access memory delay circuit and the delayed outputs are recombined by a line driver latch to provide output data pulses that are delayed, delayed and compressed, or delayed and stretched in accordance with the programmed delays and system requirements. The programmable random access memory delay circuits each comprise a random access memory used as a variable length register having an address counter operating as a ring counter.