Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

Abstract: A system and method for managing operating parameters within a system for optimal power and reliability are described. A device includes a functional unit and a corresponding reliability evaluator. The functional unit provides reliability information to one or more reliability monitors, which translate the information to reliability values. The reliability evaluator determines an overall reliability level for the system based on the reliability values. The reliability monitor compares the actual usage values and the expected usage values. When system has maintained a relatively high level of reliability for a given time interval, the reliability evaluator sends an indication to update operating parameters to reduce reliability of the system, which also reduces power consumption for the system.

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

Abstract: A system and method for managing operating parameters within a system for optimal power and reliability are described. A device includes a functional unit and a corresponding reliability evaluator. The functional unit provides reliability information to one or more reliability monitors, which translate the information to reliability values. The reliability evaluator determines an overall reliability level for the system based on the reliability values. The reliability monitor compares the actual usage values and the expected usage values. When system has maintained a relatively high level of reliability for a given time interval, the reliability evaluator sends an indication to update operating parameters to reduce reliability of the system, which also reduces power consumption for the system.

Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

Abstract: Various integrated circuits and methods of making and operating the same are disclosed. In aspect, a method of operating an integrated circuit is provided. The method includes, in a compute unit that has a first lane and a second lane, executing operations with the first lane and the second lane. The first lane and the second lane are monitored for an indicator of asynchronous operation. An input voltage of one or both of the first lane and the second lane is selectively adjusted if the indicator of asynchronous operation is detected.

Abstract: A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.

Abstract: A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.

Abstract: In accordance with some embodiments, an error checking scheme to check for an error in a memory unit during a dormant state is provided herein.

Abstract: Returning to FIG. 2, sense circuit 201 represents the circuit that must sense the signaling on an interconnect. NMOS device 202 is always on so that there is a continuous path to ground whenever PMOS driver 204 is on. Since leakage power is an order of magnitude less than static and dynamic power it can be omitted for clarity, although it should be noted that dynamic power increases with respect to line length since the interconnect capacitance increases as line length increases. Static power is due to flow of static current across the two resistances shown in FIG. 2, interconnect resistance 206 and the resistance of transistors 102 and 104 from FIG. 1, represented by the resistance of equivalent NMOS transistor 208 of FIG. 2.

Abstract: Circuit for differential current sensing with reduced static power. Embodiments of the present invention provide a reduced static power differential current sense amplifier (DCSA) that can use a self-timed shutoff system to disable the sense amplifier after sensing is done and enable the sense amplifier before the start of sensing. The current sense amplifier can include at least two cross-coupled inverters. A decoupling mechanism connected to the cross-coupled inverters can be provided. The decoupling mechanism accepts a sense enable (SE) signal that selectively enables and disables the current sense amplifier. A discharge mechanism can also be connected to the cross-coupled inverters to remove excess charge. A selectively enabled low impedance path from the cross-coupled inverters to ground can also be provided.