Patents by Inventor Wayne D. Dettloff
Wayne D. Dettloff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10840920Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: December 2, 2019Date of Patent: November 17, 2020Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Publication number: 20200212917Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: December 2, 2019Publication date: July 2, 2020Inventors: Jared L. ZERBE, Brian S. LEIBOWITZ, Hsuan-Jung SU, John Cronan EBLE, III, Barry William DALY, Lei LUO, Teva J. STONE, John WILSON, Jihong REN, Wayne D. DETTLOFF
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Patent number: 10541693Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: January 8, 2019Date of Patent: January 21, 2020Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Publication number: 20190238142Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: January 8, 2019Publication date: August 1, 2019Inventors: Jared L. ZERBE, Brian S. LEIBOWITZ, Hsuan-Jung SU, John Cronan EBLE, III, Barry William DALY, Lei LUO, Teva J. STONE, John WILSON, Jihong REN, Wayne D. DETTLOFF
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Patent number: 10211841Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: August 2, 2017Date of Patent: February 19, 2019Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Publication number: 20180083642Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: August 2, 2017Publication date: March 22, 2018Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 9748960Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: August 11, 2014Date of Patent: August 29, 2017Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 9294317Abstract: AC-coupled termination and equalization, including transmit equalization and/or receive equalization, are combined to create a high bandwidth channel that requires no special coding and consumes no or negligible DC current.Type: GrantFiled: March 15, 2013Date of Patent: March 22, 2016Assignee: Rambus Inc.Inventors: John Wilson, Lei Luo, Wayne D. Dettloff
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Publication number: 20140347108Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: August 11, 2014Publication date: November 27, 2014Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 8836394Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: GrantFiled: June 14, 2012Date of Patent: September 16, 2014Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 8743973Abstract: A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.Type: GrantFiled: May 25, 2011Date of Patent: June 3, 2014Assignee: Rambus Inc.Inventors: Lei Luo, Brian S. Leibowitz, Jared L. Zerbe, Barry W. Daly, Wayne D. Dettloff, John C. Eble, III, John Wilson
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Patent number: 8633733Abstract: A voltage mode transmitter equalizer has high efficiencies, yet consumes substantially constant supply current from the power supply and provides constant back-match impedance. The voltage mode transmitter equalizer is configured such that the output voltage of the signal to be output on a pair of transmission lines can be controlled according to the input data, but its return impedance is substantially matched to the differential impedance of the transmission lines and it draws substantially constant supply current from the power supply regardless of the output voltage of the signal. Further, an equalizer for a voltage-mode transmitter provides fine-granularity equalization settings by employing a variable pull-up conductance and a variable pull-down conductance. Conductance is varied by selectively enabling a plurality of conductance channels, at least some of which have resistance values that are distinct from one another.Type: GrantFiled: March 26, 2010Date of Patent: January 21, 2014Assignee: Rambus Inc.Inventors: Wayne D. Dettloff, John W. Poulton, John M. Wilson
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Publication number: 20130249612Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.Type: ApplicationFiled: June 14, 2012Publication date: September 26, 2013Applicant: RAMBUS INC.Inventors: Jared L. Zerbe, Brian S. Leibowitz, Hsuan-Jung Su, John Cronan Eble, III, Barry William Daly, Lei Luo, Teva J. Stone, John Wilson, Jihong Ren, Wayne D. Dettloff
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Patent number: 8531206Abstract: High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC.Type: GrantFiled: September 14, 2010Date of Patent: September 10, 2013Assignee: Rambus Inc.Inventors: Amir Amirkhany, Chaofeng Huang, Kambiz Kaviani, Wayne D. Dettloff, Kun-Yung Chang
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Publication number: 20120025800Abstract: A voltage mode transmitter equalizer has high efficiencies, yet consumes substantially constant supply current from the power supply and provides constant back-match impedance. The voltage mode transmitter equalizer is configured such that the output voltage of the signal to be output on a pair of transmission lines can be controlled according to the input data, but its return impedance is substantially matched to the differential impedance of the transmission lines and it draws substantially constant supply current from the power supply regardless of the output voltage of the signal. Further, an equalizer for a voltage-mode transmitter provides fine-granularity equalization settings by employing a variable pull-up conductance and a variable pull-down conductance. Conductance is varied by selectively enabling a plurality of conductance channels, at least some of which have resistance values that are distinct from one another.Type: ApplicationFiled: March 26, 2010Publication date: February 2, 2012Inventors: Wayne D. Dettloff, John W. Poulton, John M. Wilson
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Publication number: 20110293041Abstract: A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.Type: ApplicationFiled: May 25, 2011Publication date: December 1, 2011Inventors: Lei Luo, Brian S. Leibowitz, Jared L. Zerbe, Barry W. Daly, Wayne D. Dettloff, John C. Eble, III, John Wilson
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Publication number: 20100236644Abstract: A valve assembly may include a main housing and first and second electro-statically actuated valves. The main housing may define at least three chambers, with a first chamber configured to be coupled to a high pressure supply port, a second chamber configured to be coupled to an output port, and a third chamber configured to be coupled to a low pressure exhaust port. The first electro-statically actuated valve may be provided between the first and second chambers, and the first electro-statically actuated valve may allow or substantially block fluid communication between the first chamber and the second chamber responsive to a first electrical signal. The second electro-statically actuated valve may be provided between the second and third chambers, and the second electro-statically actuated valve may allow or substantially block fluid communication between the second chamber and the third chamber responsive to a second electrical signal. Related methods are also discussed.Type: ApplicationFiled: June 4, 2010Publication date: September 23, 2010Inventors: Kevin R. Douglas, William O. Teach, Paul W. Gibson, Donald C. Harris, Scott H. Goodwin, David E. Dausch, Wayne D. Dettloff
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Patent number: 7753072Abstract: A valve assembly may include a main housing and first and second electro-statically actuated valves. The main housing may define at least three chambers, with a first chamber configured to be coupled to a high pressure supply port, a second chamber configured to be coupled to an output port, and a third chamber configured to be coupled to a low pressure exhaust port. The first electro-statically actuated valve may be provided between the first and second chambers, and the first electro-statically actuated valve may allow or substantially block fluid communication between the first chamber and the second chamber responsive to a first electrical signal. The second electro-statically actuated valve may be provided between the second and third chambers, and the second electro-statically actuated valve may allow or substantially block fluid communication between the second chamber and the third chamber responsive to a second electrical signal. Related methods are also discussed.Type: GrantFiled: July 22, 2005Date of Patent: July 13, 2010Assignee: AFA Controls LLCInventors: Kevin R. Douglas, William O. Teach, Paul W. Gibson, Donald C. Harris, Scott H. Goodwin, David E. Dausch, Wayne D. Dettloff
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Patent number: 6960984Abstract: Methods and systems for compensating magnetic current loops provide current magnitude and phase uniformity within the magnetic current loops. A magnetic current loop is divided into k sections. Each of the k sections has a series reactance. Series reactive compensation is added to each of the k sections such that the reactive compensation substantially cancels the series reactance of each section. Adding reactive compensation to the loop that cancels the series reactance of each section of the loop provides current magnitude and phase uniformity along the loop at any given instant in time. As a result, the magnitude and phase of the magnetic field at a point in space can be controlled with precision to achieve a desired result, such as precise field cancellation or precise field generation.Type: GrantFiled: November 27, 2000Date of Patent: November 1, 2005Assignees: University of North Carolina, dBTag, Inc.Inventors: Leandra Vicci, Wayne D. Dettloff
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Patent number: 6570541Abstract: First and second spaced apart in-phase current loops at least partially overlap in the axial direction. The first and second current loops may be first and second arrays of in-phase current loops that are spaced apart and at least partially overlap in the axial direction. First and second arrays of arrays also may be provided that are spaced apart from one another and that at least partially overlap in the axial direction. Desirably high mid-field strength may be provided without violating guidelines for far field radiation in the axial direction or in the plane of the loops. A third array of in-phase current loops, an array of third in-phase current loops and/or an array of arrays of third in-phase current loops also may be provided that spaced apart from and at least partially overlapping the second loops in the axial direction, opposite the first loops.Type: GrantFiled: December 7, 2000Date of Patent: May 27, 2003Assignee: db Tag, Inc.Inventor: Wayne D. Dettloff