Abstract: A data and clock recovery system for capturing and processing serial data of a type wherein data bits of an unknown format are interleaved with clock bits utilizes a phase lock loop capable of being operated in a capture mode or a tracking mode. The data stream is compared with an internally generated reference signal, and error pulses having widths proportional to the phase error are generated. In the capture mode, these error pulses are differentially processed to produce a control voltage which varies the frequency of a VCO which in turn alters the reference frequency. In the tracking mode, phase error pulses of fixed widths are processed only if the data bits occur in fixed windows. Differential amplifying means provide adjustable gain control of the error pulses. Means are provided for digitally controlling the loop's dynamic response when switching between the capture and tracking modes.

Abstract: A digital data processor having the capability of handling more than one interrupt wherein one of the interrupts is a fast interrupt is provided. Interrupts are received by a priority network which establishes the priority of the interrupts should more than one interrupt occur at the same time. The output of the priority network is stored in a latch and the output of the latch is coupled to a vector and code logic circuit which encodes the vector address for the interrupt received. Whenever a fast interrupt is received a flag is set in a storage means so that when the system returns from interrupt it will be able to determine whether a fast interrupt had been serviced or not.