Patents by Inventor Wayne D. Kever

Wayne D. Kever has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6643828
    Abstract: A method of providing critical circuits in a library of circuits, whereby such critical circuits allows designers to apply modifications to them in a controlled manner such that the changes are easy to implement and virtually guaranteed to be correct. The invention comprises a method of performing limited modifications to such critical circuits to alter its characteristics in a controlled manner, and thereafter checking the resulting modified circuit with a circuit simulator for conformance to predetermined specifications that have been assembled for this library critical circuit.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: November 4, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Samuel D. Naffziger, Wayne D. Kever
  • Publication number: 20030145239
    Abstract: A circuit for reducing power in an on-chip cache memory on a microprocessor chip is implemented by dynamically controlling power applied to individual memory sections. Individual sections of memory are isolated from a fixed power supply by inserting one or more switches between GND and a negative connection of an individual memory section or by inserting one or more switches between VDD and a positive connection of an individual memory section. If a memory section is not accessed for a defined time, a PMU (Performance Monitor Unit) detects it and the power to that section is switched off, saving power. In addition, a software application may send information to the PMU to select the amount of cache memory needed for the particular software application.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Inventors: Wayne D. Kever, Eric S. Fetzer
  • Publication number: 20030145170
    Abstract: A system and method for optimizing the power consumption or the access time of a subdivided cache memory system is described. An adjustable voltage power supply provides power to a section of a subdivided cache. The voltage to this section may be increased, yielding a faster access time. The voltage to this section may also be decreased. Decreasing the voltage to this section decreases the power consumed by the cache memory system.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 31, 2003
    Inventor: Wayne D. Kever
  • Publication number: 20030115560
    Abstract: A method of providing critical circuits in a library of circuits, whereby such critical circuits allows designers to apply modifications to them in a controlled manner such that the changes are easy to implement and virtually guaranteed to be correct. The invention comprises a method of performing limited modifications to such critical circuits to alter its characteristics in a controlled manner, and thereafter checking the resulting modified circuit with a circuit simulator for conformance to predetermined specifications that have been assembled for this library critical circuit.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 19, 2003
    Inventors: Samuel D. Naffziger, Wayne D. Kever