Patents by Inventor Wayne D. Ward

Wayne D. Ward has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6986003
    Abstract: Multi-processor computer systems with multiple levels of cache memories are slowed down in trying to process software locks for common functions. This invention obviates the problem for the vast majority of transactions by providing an alternate procedure for handling so-called communal locks differently from ordinary software locks. The alternative procedure is not used for ordinary (non communal software lock) data and instruction transfers. The function of the CSWL (Communal SoftWare Lock) is actually accomplished at a specific cache to which an individual CSWL is mapped to, rather than sending the lock to the requesting process, which also enhances efficiency.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: January 10, 2006
    Assignee: Unisys Corporation
    Inventors: Ralph E. Sipple, Wayne D. Ward
  • Patent number: 6944863
    Abstract: In a computer system a system of exchanging tokens for queue banks is created that permits a requester to directly specify which queue bank is wanted. Only the desired queue bank is withdrawn from a queue bank repository to accomplish this and no sorting or FIFO handling of queue banks is needed. The system uses a schema similar to a coat check room, where the requester is given a token when the requestor wants to deposit a queue bank into the queue bank repository. The queue bank repository returns the queue bank when the token is returned by the requester. In its most efficient form, two machine-level instructions handle the entire operation, a withdraw instruction and a deposit instruction.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: September 13, 2005
    Assignee: Unisys Corporation
    Inventors: Wayne D. Ward, David R. Johnson, David C. Johnson, Charles R. Caldarale
  • Patent number: 6922744
    Abstract: In order to implement alternative pathways and procedures for handling a separate set of software locks, an arrangement of circuits is described. These circuits allow for generating and handling specific requests for communal software locks without additional software development through pathways and procedures separate from ordinary lock handling operations. A side door communications pathway is set up to handle the communal locks separately from the ordinary data transfer pathways through which ordinary software locks get handled. Supporting and controller circuits handle the locking and unlocking process as well as communicating results of lock requests back to requesters.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: July 26, 2005
    Assignee: Unisys Corporation
    Inventors: Ralph E. Sipple, Wayne D. Ward
  • Patent number: 6816952
    Abstract: The current invention provides an improved system and method for locking shared resources. The invention may operate in a data processing environment including a main memory system coupled to multiple instruction processors (IPs). Lock-type instructions are included within the hardware instruction set of ones of the IPs. These lock-type instructions are executed to gain access to a software-lock stored at a predetermined location within the main memory. After activating the software-lock, further, indivisible execution of the lock-type instruction causes one or more addresses associated with the software-lock to be retrieved. These addresses are used as pointers to, in turn, retrieve the data signals protected by the software-lock. Requests for the protected data signals are issued automatically by the hardware on behalf of the requesting IP, and the IP is allowed to continue instruction execution.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: November 9, 2004
    Assignee: Unisys Corporation
    Inventors: Kelvin S. Vartti, Wayne D. Ward, Hans C. Mikkelsen
  • Patent number: 6810464
    Abstract: Multi-processor computer systems with multiple levels of cache memories are given an alternate pathway for handling highly contended-for locks. These are called communal locks. The alternate pathway allows for alternate processing schemas that do not impede the performance of the overall system as is otherwise the case in such computer systems where contended-for locks bounce back and forth between contending caches, crimping storage bus bandwidth and system performance. The alternative pathway is not used for ordinary (non communal software lock) data and instruction transfers.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: October 26, 2004
    Assignee: Unisys Corporation
    Inventors: Ralph E. Sipple, Wayne D. Ward
  • Patent number: 6654875
    Abstract: Instruction processor and method supporting dual-mode execution of computer instructions. In various embodiments, certain instructions are executable in one of two modes. The first mode is compatible with the native instruction set and data words, and the second mode is an adaptation suitable for platform independent instructions. A control word RAM is addressed by the operation code of an instruction, and each word in the control word RAM includes an address into a microcode RAM. The address into the microcode RAM is manipulated in accordance with the various embodiments to reference either a first set of microcode for native instructions and data words, or a second set of microcode for execution in a platform-independent mode.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: November 25, 2003
    Assignee: Unisys Corporation
    Inventors: Thomas D. Hartnett, John S. Kuslak, Peter B. Criswell, Wayne D. Ward
  • Patent number: 6601153
    Abstract: A system and method for increasing processing performance in a computer system by asynchronously performing system activities that do not conflict with normal instruction processing, during inactive memory access periods. The computer system includes at least one instruction processor to process instructions of an instruction stream, and a memory to store data. One or more inactive data blocks in the memory are identified, and a list of addresses corresponding to the identified inactive data blocks is generated. Available computing cycles occurring during processing in the computer system are identified, such as processing stalls and idle memory write periods. The inactive data blocks associated with the list of addresses are initialized to a predetermined state, during the available computing cycles. Addresses corresponding to those initialized data blocks are then made available to the computing system to facilitate use of the data blocks.
    Type: Grant
    Filed: December 31, 1999
    Date of Patent: July 29, 2003
    Assignee: Unisys Corporation
    Inventors: Kenneth L. Engelbrecht, Hans C. Mikkelsen, Wayne D. Ward
  • Patent number: 6247064
    Abstract: A system and method for adding a queue entry containing message data to a queue shared by communicating, sequential processes includes an enqueue instruction. The enqueue instruction attaches a queue entry to either the tail or the head of the shared queue, as specified by an application programmer. Execution of the enqueue instruction includes blocking access to the queue by other processes, updating queue linkages, activating processes waiting on entries being made to the queue, monitoring interrupts, and validating the appropriate queue data structures. If desired, in lieu of adding a queue entry containing message data to the queue, the enqueue instruction inserts an event indicator into the shared queue structure, thereby providing synchronization capabilities between communicating processes.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: June 12, 2001
    Assignee: Unisys Corporation
    Inventors: Merwin H. Alferness, Charles R. Caldarale, David C. Johnson, David R. Johnson, James R. McBreen, Wayne D. Ward
  • Patent number: 6029205
    Abstract: A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry which is visible in the virtual address space of the first process. The queue entry is added to a queue by the sending process directing the processor to execute an enqueue instruction. The receiving process removes the queue entry from the queue by directing the processor to execute a dequeue instruction. The receiving process then has direct access and visibility to the contents of the queue entry without having to copy the data into its virtual address space. Instead of sending data in a queue entry, a sending process may send an event indicator and no data.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: February 22, 2000
    Assignee: Unisys Corporation
    Inventors: Merwin H. Alferness, Mark D. Aubel, Charles R. Caldarale, James W. Douglas, David C. Johnson, David R. Johnson, Joseph P. Kerzman, James R. McBreen, Hans C. Mikkelsen, Donna J. Plunkett, Richard M. Shelton, Francis A. Stephens, Wayne D. Ward
  • Patent number: 5602998
    Abstract: A system and method for removing a queue entry containing message data from a queue shared by communicating, sequential processes includes dequeue (DEQ) and dequeue or wait (DEQW) instructions. The dequeue instruction removes a queue entry from the head of the shared queue, thereby providing access to the message data contained in the queue entry to the dequeuing process. The dequeue or wait instruction removes a queue entry from the shared queue if there is one, otherwise it suspends the execution of the dequeuing process until an entry is enqueued to the queue. If an event is selected by the dequeuing process, the dequeuing process is suspended until notification of the event is detected in the shared queue. Execution of the dequeue and dequeue or wait instructions include blocking access to the queue by other processes, updating queue linkages, deactivating processes waiting on entries or events being made to the queue, monitoring interrupts, and validating the appropriate queue data structures.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: February 11, 1997
    Assignee: Unisys Corporation
    Inventors: Merwin H. Alferness, Charles R. Caldarale, David C. Johnson, David R. Johnson, James R. McBreen, Wayne D. Ward