Abstract: Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.

Abstract: A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to individual memory sections of a semiconductor memory array. Individual sections of memory are isolated from a fixed power supply by inserting one or more PFETs between a fixed power supply and a positive connection, VDD, of an individual memory section. The voltage applied to each memory section is controlled by applying a separate variable voltage to each gate of all PFETs connected to a particular memory section. If a memory section is not accessed, the voltage to that section can be lowered, saving power. If a memory section is accessed, the voltage to that section may be raised, providing more power and shortening read and write times.

Abstract: A pseudo-NMOS logic gate of an integrated circuit chip is enabled for a time interval that is substantially less than one-half a clock cycle of the integrated circuit. A latch responds to an output signal of the pseudo-NMOS logic gate for a period that is simultaneous with or slightly less than the time while the pseudo-NMOS logic gate is enabled. The latch derives an output signal commensurate with the output signal of the pseudo-NMOS logic gate while the pseudo-NMOS logic gate is enabled, until the next clock cycle occurs.