Patents by Inventor Wayne Ellis

Wayne Ellis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10399292
    Abstract: A high numerical aperture opto-mechanical scanner for writing refractive index modifications includes a fast axis scanner having a fast scanning axis. A waveform generator is electrically coupled to the fast axis scanner, and a waveform is provided by the waveform generator which defines a fast scan of the fast axis scanner. A scanning lens assembly is mechanically coupled to the fast axis scanner, the scanning lens assembly having a NA greater than 0.5 and a scanning lens motion along the fast scanning axis. A femtosecond laser is optically coupled through the scanning lens assembly to a surface of a material, creating a femtosecond laser light scanning pattern to write the refractive index modifications into the material. A method for writing refractive index modifications using a high numerical aperture opto-mechanical scanner is also described.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: September 3, 2019
    Assignee: University of Rochester
    Inventors: Wayne H. Knox, Jonathan Ellis
  • Patent number: 9878884
    Abstract: A load-hauling device includes a pair of karabiners, each having an array of pulleys, a pulley rope fixed at one end to one of the karabiners below its respective pulley array, to anchor that end of the rope, the pulley rope passing sequentially between the pulleys of each pulley array to provide a mechanical advantage at the free end of the pulley rope when pulled, a rotatable locking cam mounted between a cam yoke fixed around an end pulley of one of the pulley arrays, wherein the cam includes a cam spring to bias the cam to engage with the rope and permit movement of the rope in one direction while preventing movement of the rope in the other direction, the cam including an integral trigger and locking mechanism to selectively disengage the cam from the rope and allow the device to release a load carried thereby.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL SAFETY COMPONENTS LTD
    Inventors: Wayne Ellis, Kevin Brown
  • Patent number: 9411678
    Abstract: A method of operation in a memory device, comprising storing data in a first group of storage locations in the memory device, storing error information associated with the stored data in a second group of storage locations in the memory device, and selectively evaluating the error information based on a state of an error enable bit, the state based on whether a most recent access to the first group of storage locations involved a partial access.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 9, 2016
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Suresh Rajan, Ely Tsern, Thomas Vogelsang, Wayne Ellis
  • Patent number: 9064730
    Abstract: Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. The techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer, an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns, and an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: June 23, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Wayne Ellis, John Kim
  • Patent number: 8947965
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array, a second region coupled to a respective source line of the array, a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region, and a third region coupled to a respective carrier injection line of the array, wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: February 3, 2015
    Assignee: Micron Technology Inc.
    Inventors: Michael A. Van Buskirk, Betina Hold, Wayne Ellis
  • Publication number: 20140225171
    Abstract: Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. The techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer, an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns, and an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 14, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Wayne ELLIS, John KIM
  • Patent number: 8710566
    Abstract: Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer. The semiconductor memory device may also comprise an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. The semiconductor memory device may also comprise an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Wayne Ellis, John Kim
  • Patent number: 8315099
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: November 20, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Michael A. Van Buskirk, Betina Hold, Wayne Ellis
  • Publication number: 20110019482
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region.
    Type: Application
    Filed: July 27, 2010
    Publication date: January 27, 2011
    Applicant: Innovative Silicon ISi SA
    Inventors: Michael A. Van Buskirk, Betina Hold, Wayne Ellis
  • Publication number: 20100224924
    Abstract: Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer. The semiconductor memory device may also comprise an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. The semiconductor memory device may also comprise an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 9, 2010
    Applicant: Innovative Silicon ISi SA
    Inventors: Wayne Ellis, John Kim
  • Patent number: 7539034
    Abstract: A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: May 26, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jung Pill Kim, Jong-Hoon Oh, Oliver Kiehl, Josef Schnell, Klaus Hummler, Wayne Ellis, Octavian Beldiman, Lee Collins
  • Patent number: 7413833
    Abstract: An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: August 19, 2008
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Shahid Butt, Scott Bukofsky, Ramachandra Divakaruni, Carl Radens, Wayne Ellis
  • Publication number: 20080189480
    Abstract: A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.
    Type: Application
    Filed: February 1, 2007
    Publication date: August 7, 2008
    Inventors: Jung Pill Kim, Jong-Hoon Oh, Oliver Kiehl, Josef Schnell, Klaus Hummler, Wayne Ellis, Octavian Beldiman, Lee Collins
  • Publication number: 20080089116
    Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.
    Type: Application
    Filed: December 3, 2007
    Publication date: April 17, 2008
    Inventors: Wayne Ellis, Randy Mann, David Wager, Robert Wong
  • Publication number: 20070121370
    Abstract: A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.
    Type: Application
    Filed: November 29, 2005
    Publication date: May 31, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wayne Ellis, Randy Mann, David Wager, Robert Wong
  • Publication number: 20070001708
    Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.
    Type: Application
    Filed: September 12, 2006
    Publication date: January 4, 2007
    Applicant: International Business Machines Corporation
    Inventors: Claude Bertin, Wayne Ellis, Mark Kellogg, William Tonti, Jerzy Zalesinski, James Leas, Wayne Howell
  • Publication number: 20060124982
    Abstract: A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 15, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herbert Ho, John Barth, Ramachandra Divakaruni, Wayne Ellis, Johnathan Faltermeier, Brent Anderson, Subramanian Iyer, Deok-Kee Kim, Randy Mann, Paul Parries
  • Publication number: 20050255387
    Abstract: An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated.
    Type: Application
    Filed: May 14, 2004
    Publication date: November 17, 2005
    Applicants: Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Shahid Butt, Scott Bukofsky, Ramachandra Divakaruni, Carl Radens, Wayne Ellis
  • Patent number: D589095
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: March 24, 2009
    Inventor: Bruce Wayne Ellis
  • Patent number: D680420
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 23, 2013
    Assignee: International Safety Components Limited
    Inventor: Wayne Ellis