Abstract: The present disclosure describes a sensor interface (SIF) system placed between sensor sources and signal processors. A SIF system can include a sensor interface queue (SIFQ) coupled to a first sensor source and a second senor source, and further coupled to a first data assembler and a second data assembler. The SIFQ can include a first queue to store a first set of data packets received from the first sensor source, and a second queue to store a second set of data packets received from the second sensor source. The first set of data packets and the second set of data packets can share the same data packet format. The first data assembler can assemble the first set of data packets into first data in a first frame format, and the second data assembler can assemble the second set of data packets into second data in a second frame format.

Abstract: The present disclosure describes a sensor interface (SIF) system with clock rate matching. The system includes a sensor interface queue (SIFQ) coupled to a first sensor link and a second sensor link and including a first queue and a second queue. The first and second queues are configured to store a first set of data packets and a second set of data packets received from the first and second sensor links, respectively, where the SIFQ is configured to operate based on a different clock signal. The system also includes a first data assembler configured to assemble the first set of data packets into first data in a first frame format for processing by a first signal processor. The system further includes a second data assembler configured to assemble the second set of data packets into second data in a second frame format for processing by a second signal processor.

Abstract: The present disclosure describes a sensor interface (SIF) system with error detection and control. The system includes a sensor interface queue (SIFQ) coupled to a first sensor link and a second sensor link and including a first queue and a second queue. The system also includes a first data assembler coupled to the SIFQ and to a first signal processor. The first data assembler is configured to assemble the first set of data packets into first data in a first frame format for processing by the first signal processor and detect an error associated with assembling the first data in the first frame format. The system further includes a second data assembler coupled to the SIFQ and to a second signal processor. The second data assembler is configured to assemble the second set of data packets into second data in a second frame format for processing by the second signal processor.

Abstract: The present disclosure describes a sensor interface (SIF) system with queue overflow protection. The system includes a first queue enabler circuit coupled to a first sensor link and configured to enable a sensor interface queue (SIFQ) to receive a first set of data packets from the first sensor link. The system also includes a second queue enabler circuit coupled to a second sensor link and configured to enable the SIFQ to receive a second set of data packets from the second sensor link. The system further includes a controller coupled to the SIFQ, the first queue enabler circuit, and the second queue enabler circuit, where the controller is configured to detect an overflow in a first queue, disable, in response to the overflow, the first queue enabler circuit to stop receiving additional data packets from the first sensor link and enter a disabled state for the system.

Abstract: Embodiments relate to generating a Quality of Service (QOS) parameter indicating latency tolerance of an image signal processor by determining and processing latency tolerance values of its individual pipeline circuits. At least a subset of the pipeline circuits that performs image processing functions generates their individual latency tolerance values. Each of the individual latency tolerance value is determined as a difference between a sampling time at which an operation is performed on certain pixel data and a latest time by which the operation should be performed on the same pixel data. The individual latency tolerance values generated in this manner provides a mechanism to determine the QoS parameter relevant to an image signal processing scheme that involves access to memory multiple times to save and retrieve intermediate pixel data and process incoming pixel data in a real-time manner.

Abstract: Embodiments relate to detecting a timeout error on receipt of valid pixel data from an image sensor by a sensor interface circuit. When the valid pixel data is not timely received at the sensor interface circuit, a timeout error signal is generated by the sensor interface circuit. A time limit for determining the timeout error signal may be defined by a global clock that provides a clock signal to the sensor interface circuit and other circuits. As a result, the sensor interface circuit generates a dummy frame and sends out the dummy frame to subsequent circuits so that the timeout error does not bottleneck subsequent processing stages. In contrast, if the valid pixel data is timely received, sensor data received from the image sensor is unpacked into a frame of pixels.

Abstract: Embodiments relate to detecting a timeout error on receipt of valid pixel data from an image sensor by a sensor interface circuit. When the valid pixel data is not timely received at the sensor interface circuit, a timeout error signal is generated by the sensor interface circuit. A time limit for determining the timeout error signal may be defined by a global clock that provides a clock signal to the sensor interface circuit and other circuits. As a result, the sensor interface circuit generates a dummy frame and sends out the dummy frame to subsequent circuits so that the timeout error does not bottleneck subsequent processing stages. In contrast, if the valid pixel data is timely received, sensor data received from the image sensor is unpacked into a frame of pixels.

Abstract: A system and method for generating pixels for a display device. The system may include a sample buffer for storing a plurality samples in a memory, a sample cache for caching recently accessed samples, and a sample filter unit for filtering one or more samples to generate a pixel. The generated pixels may then be stored in a frame buffer or provided to a display device. The method operates to take advantage of the common samples shared by neighboring pixels in both the x and y directions for reduced sample buffer accesses and improved performance. The method involves reading samples from the memory that correspond to pixels in a plurality of neighboring scan lines, and possibly also to multiple pixels in each of these scan lines. The samples may be stored in a cache memory and then accessed from the cache memory for filtering. The method maximizes use of the common samples shared by neighboring pixels in both the x and y directions.

Abstract: In one embodiment, a computer system includes a first component configured to output data on a bus in response to a request for data from a second component. The data output by the first component may include both the requested data and unrequested data, and the unrequested data may have an unpredictable value. A controller coupled to the bus may be configured to replace the unrequested data with data that has a predictable value. A signature analysis register included in the second component is configured to capture the requested data and the predictable data output by the controller. Thus, the signature captured in the second component may be predictable, despite the unpredictable data output by the first component.

Abstract: A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback bus has a plurality of logic units coupled in a series. Each logic unit couples to a corresponding one of the computational units. The read control unit couples to each of the computational units through a corresponding load line, and is configured to assert a load signal on one of the load lines in response to a register read request. Each of the computational units is configured to transmit a data value from a selected register onto the readback bus in response to detecting an assertion of the load signal on its corresponding load line.

Abstract: An integrated circuit may include several components, one or more interfaces, an interconnect (e.g., a bus), and a controller. The components may each be configured to assert a read request to read data stored externally to the integrated circuit. The interfaces may be configured to output the read request asserted by one of the components and to receive data in response to outputting the request. The interconnect may be coupled to perform one or more data transactions to transmit the data from one of the interfaces to one or more of the components. In response to the read request asserted by one of the components, the controller may inhibit performance of a read transaction initiated by the read request dependent upon a comparison of a total number of outstanding data transactions to a maximum allowable number of outstanding data transactions.

Abstract: An integrated circuit may include several components, one or more interfaces, an interconnect (e.g., a bus), and a controller. The components may each be configured to assert a read request to read data stored externally to the integrated circuit. The interfaces may be configured to output the read request asserted by one of the components and to receive data in response to outputting the request. The interconnect may be coupled to perform one or more data transactions to transmit the data from one of the interfaces to one or more of the components. In response to the read request asserted by one of the components, the controller may inhibit performance of a read transaction initiated by the read request dependent upon a comparison of a total number of outstanding data transactions to a maximum allowable number of outstanding data transactions.

Abstract: In one embodiment, a computer system includes a first component configured to output data on a bus in response to a request for data from a second component. The data output by the first component may include both the requested data and unrequested data, and the unrequested data may have an unpredictable value. A controller coupled to the bus may be configured to replace the unrequested data with data that has a predictable value. A signature analysis register included in the second component is configured to capture the requested data and the predictable data output by the controller. Thus, the signature captured in the second component may be predictable, despite the unpredictable data output by the first component.

Abstract: A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback bus has a plurality of logic units coupled in a series. Each logic unit couples to a corresponding one of the computational units. The read control unit couples to each of the computational units through a corresponding load line, and is configured to assert a load signal on one of the load lines in response to a register read request. Each of the computational units is configured to transmit a data value from a selected register onto the readback bus in response to detecting an assertion of the load signal on its corresponding load line.

Abstract: A system and method for generating pixels for a display device. The system may include a sample buffer for storing a plurality samples in a memory, a sample cache for caching recently accessed samples, and a sample filter unit for filtering one or more samples to generate a pixel. The generated pixels may then be stored in a frame buffer or provided to a display device. The method operates to take advantage of the common samples shared by neighboring pixels in both the x and y directions for reduced sample buffer accesses and improved performance. The method involves reading samples from the memory that correspond to pixels in a plurality of neighboring scan lines, and possibly also to multiple pixels in each of these scan lines. The samples may be stored in a cache memory and then accessed from the cache memory for filtering. The method maximizes use of the common samples shared by neighboring pixels in both the x and y directions.

Abstract: A graphics system configured to perform programmable filtering of samples to generate pixel values. The graphics system comprises a frame buffer, an accelerator unit and a video output processor. The accelerator unit receives graphics primitives, renders samples for the graphics primitives, and stores the rendered samples into a sample area of the frame buffer. The accelerator unit subsequently reads the samples from the sample area of the frame buffer, and filters the samples with a programmable filter having a programmable support region. The resulting pixel values are stored in a pixel area of the frame buffer. The video output processor reads the pixel values from the pixel area and converts the pixel values into a video signal which is provided to a video output port.

Abstract: A graphics system configured to perform programmable filtering of samples to generate pixel values. The graphics system comprises a frame buffer, an accelerator unit and a video output processor. The accelerator unit receives graphics primitives, renders samples for the graphics primitives, and stores the rendered samples into a sample area of the frame buffer. The accelerator unit subsequently reads the samples from the sample area of the frame buffer, and filters the samples with a programmable filter having a programmable support region. The resulting pixel values are stored in a pixel area of the frame buffer. The video output processor reads the pixel values from the pixel area and converts the pixel values into a video signal which is provided to a video output port.