Patents by Inventor Wayne F. Ellis
Wayne F. Ellis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11948619Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: March 9, 2023Date of Patent: April 2, 2024Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Publication number: 20230282266Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: March 9, 2023Publication date: September 7, 2023Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Patent number: 11621030Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: January 4, 2022Date of Patent: April 4, 2023Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Publication number: 20220254407Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: January 4, 2022Publication date: August 11, 2022Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Publication number: 20220223224Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: ApplicationFiled: December 20, 2021Publication date: July 14, 2022Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
-
Patent number: 11250901Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: November 24, 2020Date of Patent: February 15, 2022Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Patent number: 11211139Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: GrantFiled: March 19, 2020Date of Patent: December 28, 2021Assignee: Rambus Inc.Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
-
Publication number: 20210174865Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: November 24, 2020Publication date: June 10, 2021Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Patent number: 10878878Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: March 20, 2020Date of Patent: December 29, 2020Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Publication number: 20200312422Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: ApplicationFiled: March 19, 2020Publication date: October 1, 2020Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
-
Publication number: 20200294577Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: March 20, 2020Publication date: September 17, 2020Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Patent number: 10672450Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: September 24, 2018Date of Patent: June 2, 2020Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Patent number: 10622053Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: February 14, 2019Date of Patent: April 14, 2020Assignee: Rambus inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Patent number: 10614869Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: December 28, 2018Date of Patent: April 7, 2020Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Patent number: 10600497Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.Type: GrantFiled: December 19, 2017Date of Patent: March 24, 2020Assignee: Rambus Inc.Inventors: Yohan U. Frans, Wayne F. Ellis, Akash Bansal
-
Patent number: 10431290Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: GrantFiled: September 24, 2018Date of Patent: October 1, 2019Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Publication number: 20190180813Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: February 14, 2019Publication date: June 13, 2019Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Publication number: 20190139598Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Patent number: 10262718Abstract: In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.Type: GrantFiled: December 27, 2017Date of Patent: April 16, 2019Assignee: Rambus Inc.Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
-
Patent number: 10198314Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.Type: GrantFiled: May 22, 2014Date of Patent: February 5, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, Suresh Rajan, Brent Haukness, Scott C. Best, Wayne F. Ellis