Abstract: The disclosed embodiments disclose techniques for performing physical domain error isolation and recovery in a multi-domain system, where the multi-domain system includes two or more processor chips and one or more switch chips that provide connectivity and cache-coherency support for the processor chips, and the processor chips are divided into two or more distinct domains. During operation, one of the switch chips determines a fault in the multi-domain system. The switch chip determines an originating domain that is associated with the fault, and then signals the fault and an identifier for the originating domain to its internal units, some of which perform clearing operations that clear out all traffic for the originating domain without affecting the other domains of the multi-domain system.

Abstract: The disclosed embodiments disclose techniques for performing physical domain error isolation and recovery in a multi-domain system, where the multi-domain system includes two or more processor chips and one or more switch chips that provide connectivity and cache-coherency support for the processor chips, and the processor chips are divided into two or more distinct domains. During operation, one of the switch chips determines a fault in the multi-domain system. The switch chip determines an originating domain that is associated with the fault, and then signals the fault and an identifier for the originating domain to its internal units, some of which perform clearing operations that clear out all traffic for the originating domain without affecting the other domains of the multi-domain system.

Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g.

Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g.

Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g.

Abstract: A method and apparatus for performing virtualized parsing of an XML document. A document is divided into multiple segments, which may correspond to separate packets containing portions of the document, disk blocks, memory pages, etc. For each segment, a processor operating within an XML accelerator initiates parsing by identifying to a hardware parsing unit the document segment, a symbol table for the document and a location for storing state information regarding the parsing. Each segment is parsed in sequence, and the state information of the parsing is stored after each segment is completed, for retrieval when the next segment is to be parsed.

Abstract: A hardware unit for parsing an XML document includes embedded logic or circuitry for accessing the document, decoding it to change a character set, validating individual characters of the document, extracting tokens, maintaining a symbol table and generating binary token headers to describe the document's structure and convey the document's data to an application. Tokenization, the process of identifying tokens and generating token headers, may be controlled by a finite state machine that recognizes XML delimiters in the document's markup and activates state transitions based on the current state and the recognized delimiter. The parser unit may be implemented within a hardware XML accelerator that includes a processor, a DMA engine, a cryptographic engine, memory (e.g., for storing a document, maintaining a symbol table) and various interfaces (e.g., network, memory, bus).

Abstract: A hardware finite state machine for facilitating the processing of an XML (Extensible Markup Language) document or other structured data stream. An accelerator is implemented in hardware to enable fast processing of a document (or a segment thereof). The accelerator includes a finite state machine that embodies a ternary CAM (Content-Addressable Memory) and associated RAM (Random Access Memory). Processing of the document is divided into multiple states, with each state transition defined by a markup delimiter that triggers the transition. The CAM is programmed with entries containing the processing states and, for each possible transition from that state, a pattern for matching delimiters that trigger the possible transitions. For a CAM entry matching the current processing state and a sequence of characters from the document, which may contain a delimiter, the associated RAM identifies the next state and any action to be taken (e.g., to shift the sequence of characters).

Abstract: One embodiment of the present invention provides a system that facilitates packet communication between a device within a computing system and one or more additional devices of the computing system. The system receives either a point-to-point packet or a broadcast packet from the devices and inspects the header of the packet to determine the type of packet. The system also examines the state of the computing system to determine whether the state of the computer system is broadcast preferred or point-to-point only. If the type of the packet is broadcast and the state of the computing system is broadcast preferred, the system sends the packet to all of the additional devices. If the type of the packet is broadcast and the state of the computing system is point-to-point only, the system delays sending the packet until the state of the computing system changes to broadcast preferred.