Abstract: A warmswap operation to replace modules in a mirrored cache system has been accomplished by disabling mirrored write operations in the cache system; testing the replacement memory module in the cache system; and restoring the mirrored data in the cache system. The restoring operation is accomplished by first quiescing write operations to stop writing data in the cache system not backed up in non-volatile data storage. Then data is copied from surviving memory modules to the replacement module, and the cooperative interaction of the surviving memory modules with the replacement memory module is validated. The validating operation verifies the cache modules are ready and the controllers are synchronized. After validation the quiesced write operations are un-quiesced, and mirrored-write operations for the cache system are enabled.

Abstract: An apparatus and method for synchronizing a cache mode in a cache memory system in a computer to protect cache operations. The cache memory system has a first controller and a second controller and two cache modules and operates in a plurality of cache modes. The cache mode is stored as metadata in the cache modules and is detected by the first controller to determine the cache mode. Lock signals in the first controller are set in accordance with the cache mode detected to set the cache mode state in the first controller. The second controller copies the cache mode state from the first controller to synchronize both controllers in the same cache mode state. After a failure of the second controller, the first controller may lock access to both caches to recover data previously accessed by the second controller. The second controller restarts and copies the cache mode state from the first controller, so that both controllers return to the cache mode state prior to the failure of the second controller.

Abstract: A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.

Abstract: An improved method for testing a large memory array of a digital computer system during system initialization or reset. First, the memory test method checks the whole memory array for addressing faults, and then a first portion of the memory array for both address line and data failures. While operational firmware is loaded into and begins to execute from the tested first portion, the remaining address locations of the array are tested in a background task. Beginning at the last address of the first portion, sequential portions of memory array are tested and released to the functional code as they have been tested.