Patents by Inventor Wayne Lai

Wayne Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948619
    Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: April 2, 2024
    Assignee: Rambus Inc.
    Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
  • Publication number: 20240096387
    Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 21, 2024
    Applicant: Rambus Inc.
    Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
  • Patent number: 11931820
    Abstract: Systems and techniques are directed to a Swappable Retractable Tool Tip (SRTT), which is designed as a next generation of friction stir welding tools and retractable tool tips. The disclosed SRTT may be “swappable,” having different types of retractable tool tips that can be assembled and employed as a part of the SRTT. A SRTT system can include at least: a blank tool holder, a piston, and a retractable tool tip. In operation, the blank tool holder allows air to flow to cause movement of the piston and the retractable tool tip. For example, compressed air can push up on the piston and the retractable tool tip, retracting it into a “home” position inside of the blank tool holder. Also, the SRTT can include springs that push down on the piston and the retractable tool tip, extending the tip into an “extended” position outside of the blank tool holder.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: March 19, 2024
    Assignee: MERCURY MISSION SYSTEMS, LLC
    Inventors: Kang Lee, Matthew Neil, Wayne Chan, Anthony Lai, Andrew Kostrzewski
  • Patent number: 11688691
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Cheng Lin, Cheng-Chi Chuang, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Wayne Lai
  • Publication number: 20210183772
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.
    Type: Application
    Filed: February 1, 2021
    Publication date: June 17, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Cheng LIN, Cheng-Chi CHUANG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Ting YANG, Wayne LAI
  • Patent number: 10930595
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Cheng Lin, Cheng-Chi Chuang, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Wayne Lai
  • Publication number: 20190096809
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.
    Type: Application
    Filed: March 28, 2018
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Cheng Lin, Cheng-Chi Chuang, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Wayne Lai
  • Publication number: 20050058626
    Abstract: A general method for vaccinating against any pathogen is presented. The method utilizes expression library immunization, where an animal is inoculated with an expression library constructed from fragmented genomic DNA of the pathogen. All potential epitopes of the pathogen's proteins are encoded in its DNA, and genetic immunization is used to directly introduce one or more expression library clones to the immune system, producing an immune response to the encoded protein. Inoculation of expression libraries representing portions of the Mycoplasma pulmonis genome was shown to protect mice from subsequent challenge by this natural pathogen. Protection against Listeria was also obtained using the method.
    Type: Application
    Filed: January 29, 2004
    Publication date: March 17, 2005
    Inventors: Stephen Johnston, Michael Barry, Wayne Lai