Abstract: The present disclosure relates to methods of manufacture of piezoelectric ceramic transducers useable, for example, in an ultrasound probe, using a poling process. The poling is accomplished without contacting transducer elements and by subjecting the piezoelectric ceramic transducer to a corona discharge. The disclosure further describes a system for poling a transducer comprising at least one piezoelectric ceramic component or transducer assembly, a ground plane comprising an electrical polarity, and a corona source connected to a first power source configured to supply a first voltage to the corona source having an electrical polarity opposite the electrical polarity of the ground plane. The at least one piezoelectric ceramic component or transducer assembly is positioned between the corona source and the ground plane within a chamber.

Abstract: The present disclosure relates to methods of manufacture of piezoelectric ceramic transducers useable, for example, in an ultrasound probe, using a poling process. The poling is accomplished without contacting transducer elements and by subjecting the piezoelectric ceramic transducer to a corona discharge. The disclosure further describes a system for poling a transducer comprising at least one piezoelectric ceramic component or transducer assembly, a ground plane comprising an electrical polarity, and a corona source connected to a first power source configured to supply a first voltage to the corona source having an electrical polarity opposite the electrical polarity of the ground plane. The at least one piezoelectric ceramic component or transducer assembly is positioned between the corona source and the ground plane within a chamber.

Abstract: Reconfigurable Integrated Circuit with On-Chip Configuration Generation A circuit and method are provided in which reconfiguration is achieved through the modification of a dynamic data path using configuration information generated on the basis of run-time variables. Rather than storing a plurality of pre-set configurations, this can allow configurations optimized to processing tasks to be implemented during operation.

Abstract: Reconfigurable Integrated Circuit with On-Chip Configuration Generation A circuit and method are provided in which reconfiguration is achieved through the modification of a dynamic data path using configuration information generated on the basis of run-time variables. Rather than storing a plurality of pre-set configurations, this can allow configurations optimised to processing tasks to be implemented during operation.

Abstract: A predicate register is assigned as an exception handling predicate register. An exception may be detected when executing the machine readable instructions. An exception state for the exception is stored in the exception handling predicate register.

Abstract: A method includes generating an N-bit generated hash key for an M-bit search key. A data value associated with a matching hash key stored in a content addressable memory is retrieved. The matching hash key is then validated. The content addressable memory supports 2k entries, wherein M>N>k.

Abstract: One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.

Abstract: A system for managing battery temperature is described. The system may include a cooling system which may include a fluid. A cabin circulation subsystem may be coupled to the cooling subsystem and may utilize the fluid for cabin cooling. A separate battery circulation subsystem may also may also be coupled to the cooling subsystem so that it may additionally utilize the fluid for battery cooling. A control may be present in order to regulate movement of the fluid to the cabin circulation subsystem and/or to the battery circulation subsystem.

Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.

Abstract: A design system for generating configuration information and associated executable code based on a customisation specification, which includes application information including application source code and customisation information including design constraints, for implementing an instruction processor using re-programmable hardware, the system comprises a template generator for generating a template for each processor style identified as a candidate for implementation; an analyser for analysing instruction information for each template and determining instruction optimisations; a compiler for compiling the application source code to include the instruction optimisations and generate executable code; an instantiator for analysing architecture information for each template, determining architecture optimisations and generating configuration information including the architecture optimisations; and a builder for generating device-specific configuration information from the configuration information including the

Abstract: The present invention relates to the design-time and run-time environments of instruction processors implemented in re-programmable hardware. In one aspect the present invention provides a design system for generating configuration information and associated executable code base on a customization specification, which includes application information including application source code and customization information including design constraints, for implementing an instruction processor using re-progammable hardware, the system comprising: a template generator; an analyzer; a compiler; an instantiator, and a builder. In another aspect the present invention provides a management system for managing run-time re-configuration of an instruction processor implemented using re-programmable hardware, comprising: a configuration library; a code library; a loader; a loader controller; a run-time monitor; an optimization determiner; and an optimization instructor.

Abstract: A method includes generating an N-bit generated hash key for an M-bit search key. A data value associated with a matching hash key stored in a content addressable memory is retrieved. The matching hash key is then validated. The content addressable memory supports 2k entries, wherein M>N>k.

Abstract: One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.

Abstract: A system for managing battery temperature is described. The system may include a cooling system which may include a fluid. A cabin circulation subsystem may be coupled to the cooling subsystem and may utilize the fluid for cabin cooling. A separate battery circulation subsystem may also may also be coupled to the cooling subsystem so that it may additionally utilize the fluid for battery cooling. A control may be present in order to regulate movement of the fluid to the cabin circulation subsystem and/or to the battery circulation subsystem.

Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.

Abstract: The present invention relates to the design-time and run-time environments of instruction processors implemented in re-programmable hardware. In one aspect the present invention provides a design system for generating configuration information and associated executable code base on a customisation specification, which includes application information including application source code and customisation information including desgn constraints, for implementing an instruction processor using re-progammable hardware, the system comprising: a template generator; an analyser; a compiler; an instantiator, and a builder. In another aspect the present invention provides a management system for managing run-time re-configuration of an instruction processor implemented using re-programmable hardware, comprising: a configuration library; a code library; a loader; a loader controller; a run-time monitor; an optimisation determiner; and an optimisation instructor.