Abstract: Each processor in a multi-processor system includes a process page-table-base register and a system page-table-base register. Each register identifies a different page frame containing a different instance of a top-level subtable in a multi-level page table, and both instances' contents map their respective, different page frames to the same virtual page. A first of the instances, to which the process page-table-base register refers, is used to translate virtual addresses in a process-private range, while the second instance is used for shared-range translation. When a context switch occurs, the content of the process page-table-base register is changed in accordance with the process to whose operation the processor is turning, but that of the system page-table-base register remains unchanged.

Abstract: An error recovery method and apparatus has specific application in a networking arrangement having a plurality of individual processing nodes which communicate via shared memory space. For error recovery, the system uses a reliable error count, the value of which is maintained by all of the nodes. When an error is detected, the error count is incremented, and all of the active nodes are provided with the new error count. Any of the nodes can run the error recovery method, and may gain exclusive access to the network by acquiring an error recovery spinlock. Once the spinlock is acquired, the node holding the spinlock increments the error count and confirms that all active nodes have received the new error count. The spinlock is thereafter released.

Abstract: A method of remote debugging comprises a first computer system that communicates with a second computer using a network connection. The first computer system controls the remote debugging and comprises a first operating system. The second computer system comprises a second operating system and software being tested. User input, in the form of debug commands, is received using a remote debugger in the first computer system to control the remote debugging session. The remote debugger translates a debug command into messages that are sent from the first computer system to the second computer system. The messages correspond to tasks that the target computer system performs to complete the debug command. During debugging, the target computer system transitions between polling or stopped mode and interrupt-driven mode by transitioning both the target operating system and network hardware in the target computer system that interfaces with the network.

Abstract: A network of processors synchronize modification of a common data structure stored in an asymmetric reflective memory by using a queue. A first processor stores a queue element in a global write-only address space of the reflective memory, the reflective memory to copy the queue element to a local read/write address space of a second processor. The first processor also stores a queue header in the global write-only address space. In response to detecting the queue element, the second processor reads the queue header and then overwrites the queue header with a zero. The reading and writing of the queue header are performed atomically in the local read/write address space of the second processor. The second processor processes the queue element, and marks the queue element as processed in the global address space of the reflective memory.