Abstract: An apparatus includes a substrate, a capacitance die and an exciter die. The capacitance die is generally mounted on the substrate and may be configured to vary a frequency of a signal in an inductor. The exciter die is generally mounted on the substrate and may be configured to excite the signal. A particular one of the capacitance die and the exciter die may be fabricated with a die mask that has a plurality of available designs. The available designs generally customize the particular die to a plurality of configurations respectively. The capacitance die, the exciter die and the inductor may form a voltage-controlled oscillator.

Abstract: An apparatus includes a channel layer, a first layer, a hole barrier layer and a second layer. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valence band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally forms a field effect transistor.

Abstract: An apparatus comprising a channel layer, a first layer, a hole barrier layer and a second layer is disclosed. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valance band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally comprises a field effect transistor.

Abstract: An apparatus having a substrate, a first die and a second die is disclosed. The substrate may include a circuit having an inductance. The first die may be (i) mounted on the substrate, (ii) connected to the circuit and (iii) configured to control a frequency of an oscillation of a signal in the circuit. The frequency is generally varied by adjusting a voltage in the first die. The second die may be (i) mounted on the substrate, (ii) connected to the circuit and (iii) configured to excite the signal. The apparatus generally forms a voltage-controlled oscillator.

Abstract: An apparatus having a substrate with an inductor, a first die and a second die is disclosed. The first die may be (i) mounted on the substrate, (ii) configured to vary a frequency of a signal in the inductor, and (iii) fabricated with multiple first masks. The second die may be (i) mounted on the substrate, (ii) configured to excite the signal, and (iii) fabricated with multiple second masks. A particular one of the first masks generally has several designs that customize the first die to several configurations respectively. A particular one of the second masks may have several designs that customize the second die to several configurations respectively. The first die, the second die and the inductor may form a voltage-controlled oscillator. A selected first design and a selected second design generally establish multiple performances of the voltage-controlled oscillator.

Abstract: An apparatus having a substrate with an inductor, a first die and a second die is disclosed. The first die may be (i) mounted on the substrate, (ii) configured to vary a frequency of a signal in the inductor, and (iii) fabricated with multiple first masks. The second die may be (i) mounted on the substrate, (ii) configured to excite the signal, and (iii) fabricated with multiple second masks. A particular one of the first masks generally has several designs that customize the first die to several configurations respectively. A particular one of the second masks may have several designs that customize the second die to several configurations respectively. The first die, the second die and the inductor may form a voltage-controlled oscillator. A selected first design and a selected second design generally establish multiple performances of the voltage-controlled oscillator.

Abstract: An apparatus having a substrate, a first die and a second die is disclosed. The substrate may include a circuit having an inductance. The first die may be (i) mounted on the substrate, (ii) connected to the circuit and (iii) configured to control a frequency of an oscillation of a signal in the circuit. The frequency is generally varied by adjusting a voltage in the first die. The second die may be (i) mounted on the substrate, (ii) connected to the circuit and (iii) configured to excite the signal. The apparatus generally forms a voltage-controlled oscillator.

Abstract: An apparatus having a detector and a circuit is disclosed. The detector may be configured to generate a control signal in response to a voltage level of an input signal. The circuit may be configured to (i) connect the input signal to a reference signal with a first impedance in response to the control signal in an asserted state and (ii) connect the input signal to the reference signal with a second impedance in response to the control signal in a deasserted state. One or more transistors in the circuit are generally biased to an off state while the control signal is in the deasserted state.

Abstract: Embodiments of apparatuses, articles, methods, and systems for a bias network providing a stable transient response are generally described herein. Other embodiments may be described and claimed.

Abstract: A bias circuit that includes a rectifier having an input, an output and a DC control voltage input, wherein the rectifier is configured to produce the rectifier output, while providing a substantially high input impedance at the rectifier input, a rectified voltage from an alternating input signal applied at the rectifier input; and a bias extractor having an extractor input, a control voltage input and an extractor output, coupled to the rectifier output, and being configured to produce at the extractor output a DC voltage that is greater in magnitude than the DC control voltage input.

Abstract: An integrated circuit package houses and connects to a die to form an integrated circuit with internal matching. The package comprises a lead frame comprising at least one transmission line, a die paddle, and at least one input lead and at least one output lead. Bond wires connect select locations along the at least one transmission line to ground through impedance matching circuit components located within the integrated circuit to provide an impedance matching network associated with at least one of the output leads. The package may also substantially encapsulate the lead frame, while exposing the die paddle and the input/output leads.

Abstract: A bias circuit that includes a rectifier having an input, an output and a DC control voltage input, wherein the rectifier is configured to produce the rectifier output, while providing a substantially high input impedance at the rectifier input, a rectified voltage from an alternating input signal applied at the rectifier input; and a bias extractor having an extractor input, a control voltage input and an extractor output, coupled to the rectifier output, and being configured to produce at the extractor output a DC voltage that is greater in magnitude than the DC control voltage input.

Abstract: An integrated circuit package houses and connects to a die to form an integrated circuit with internal matching. The package comprises a lead frame comprising at least one transmission line, a die paddle, and at least one input lead and at least one output lead. Bond wires connect select locations along the at least one transmission line to ground through impedance matching circuit components located within the integrated circuit to provide an impedance matching network associated with at least one of the output leads. The package may also substantially encapsulate the lead frame, while exposing the die paddle and the input/output leads.