Patents by Inventor Wayne Melvin Barrett
Wayne Melvin Barrett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11645215Abstract: A plurality of virtual processor threads are executed on the plurality of physical processor threads. In a data structure, information pertaining to a plurality of interrupt sources in the data processing system is maintained. The information includes a historical scope of transmission of interrupt commands for an interrupt source. Based on an interrupt request from an interrupt source, an interrupt master transmits a first interrupt bus command on an interconnect fabric of the data processing system to poll one or more interrupt snoopers regarding availability of one or more of the virtual processor threads to service an interrupt. The interrupt master updates the scope of transmission specified in the data structure based on a combined response to the first interrupt bus command. The interrupt master applies the scope of transmission specified in the data structure to a subsequent second interrupt bus command for the interrupt source.Type: GrantFiled: June 11, 2021Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Florian Auernhammer, Wayne Melvin Barrett, David A. Shedivy
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Publication number: 20220398204Abstract: A plurality of virtual processor threads are executed on the plurality of physical processor threads. In a data structure, information pertaining to a plurality of interrupt sources in the data processing system is maintained. The information includes a historical scope of transmission of interrupt commands for an interrupt source. Based on an interrupt request from an interrupt source, an interrupt master transmits a first interrupt bus command on an interconnect fabric of the data processing system to poll one or more interrupt snoopers regarding availability of one or more of the virtual processor threads to service an interrupt. The interrupt master updates the scope of transmission specified in the data structure based on a combined response to the first interrupt bus command. The interrupt master applies the scope of transmission specified in the data structure to a subsequent second interrupt bus command for the interrupt source.Type: ApplicationFiled: June 11, 2021Publication date: December 15, 2022Inventors: Florian Auernhammer, Wayne Melvin Barrett, David A. Shedivy
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Publication number: 20220398130Abstract: Asynchronous completion notification is provided in a data processing system including one or more cores each executing one or more threads. A hardware unit of the data processing system receives and enqueues a request for processing and a source tag indicating at least a thread and core that issued the request. The hardware unit maintains a pointer to a completion area in a memory space. The completion area includes a completion granule for the hardware unit and thread. The hardware unit performs the processing requested by the request and computes an address of the completion granule based on the pointer and the source tag. The hardware unit then provides completion notification for the request by updating the completion granule with a value indicating a completion status.Type: ApplicationFiled: June 11, 2021Publication date: December 15, 2022Inventors: Florian Auernhammer, David A. Shedivy, Daniel Wind, Wayne Melvin Barrett
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Patent number: 8804960Abstract: A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.Type: GrantFiled: February 22, 2010Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Kenneth Michael Valk
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Patent number: 8275922Abstract: A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.Type: GrantFiled: February 22, 2010Date of Patent: September 25, 2012Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Kenneth Michael Valk
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Patent number: 8103930Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.Type: GrantFiled: May 27, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 8010682Abstract: In a shared memory architecture, early coherency indication is used to notify a communications interface, prior to the data for a memory request is returned, and prior to updating a coherency directory in response to the memory request, that the return data can be used by the communications interface when it is received thereby from a source of the return data. By doing so, the communications interface can often begin forwarding the return data over its associated communication link with little or no latency once the data is retrieved from its source. In addition, the communications interface is often no longer required to wait for updating of the coherency directory to complete prior to forwarding the return data over the communication link. As such, the overall latency for handling the memory request is typically reduced.Type: GrantFiled: December 28, 2004Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, David Alan Shedivy, Kenneth Michael Valk, Brian T. Vanderpool
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Publication number: 20110206141Abstract: A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.Type: ApplicationFiled: February 22, 2010Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wayne Melvin Barrett, Kenneth Michael Valk
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Publication number: 20110208954Abstract: A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.Type: ApplicationFiled: February 22, 2010Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wayne Melvin Barrett, Kenneth Michael Valk
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Patent number: 7890708Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.Type: GrantFiled: February 12, 2008Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Brian T. Vanderpool
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Patent number: 7536514Abstract: An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data if the source has an exclusive copy of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources.Type: GrantFiled: September 13, 2005Date of Patent: May 19, 2009Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Kenneth Michael Valk, Brian T. Vanderpool
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Publication number: 20090028073Abstract: A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.Type: ApplicationFiled: August 14, 2008Publication date: January 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wayne Melvin Barrett, Dong Chen, Paul William Coteus, Alan Gene Gara, Rory Jackson, Gerard Vincent Kopcsay, Ben Jesse Nathanson, Pavlos Michael Vranas
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Patent number: 7426672Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.Type: GrantFiled: April 28, 2005Date of Patent: September 16, 2008Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Philip Rogers Hillier, III, Joseph Allen Kirscht, Elizabeth A. McGlone
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Publication number: 20080222489Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.Type: ApplicationFiled: May 27, 2008Publication date: September 11, 2008Applicant: International Business Machines CorporationInventors: Wayne Melvin Barrett, Philip Rogers Hillier, Joseph Allen Kirscht, Elizabeth A. McGlone
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Patent number: 7418068Abstract: A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.Type: GrantFiled: February 25, 2002Date of Patent: August 26, 2008Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Dong Chen, Paul William Coteus, Alan Gene Gara, Rory Jackson, Gerard Vincent Kopcsay, Ben Jesse Nathanson, Paylos Michael Vranas, Todd E. Takken
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Patent number: 7392353Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.Type: GrantFiled: December 3, 2004Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Brian T. Vanderpool
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Publication number: 20080140893Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.Type: ApplicationFiled: February 12, 2008Publication date: June 12, 2008Applicant: International Business Machines CorporationInventors: Wayne Melvin Barrett, Brian T. Vanderpool
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Publication number: 20040114698Abstract: A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.Type: ApplicationFiled: February 5, 2004Publication date: June 17, 2004Inventors: Wayne Melvin Barrett, Dong Chen, Paul William Coteus, Alan Gene Gara, Rory Jackson, Gerard Vincent Kopcsay, Ben Jesse Nathanson, Paylos Michael Vranas
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Patent number: 6185646Abstract: A data transfer method and apparatus are provided for transferring data in a computer system on a high-speed synchronous multi-drop bus. Multiple devices including at least a first group of a plurality of devices and a second group of at least one device are connected to the high-speed synchronous multi-drop bus. To transfer data between devices in the first group, a first unidirectional data valid signal is applied to each device in the second group. The data from a sending device in the first group is transferred to a designated device in the second group. A second unidirectional data valid signal is applied to each device in the first group. The data is transferred from the designated device in the second group to a selected device in the first group.Type: GrantFiled: December 3, 1997Date of Patent: February 6, 2001Assignee: International Business Machines CorporationInventors: Wayne Melvin Barrett, Gerald Keith Bartley, Douglas A. Baska, Paul Eric Dahlen, Robert Allen Drehmel, Kenneth Claude Hinz, James Anthony Marcella