Abstract: A rotating launcher system includes a plurality of rocket or missile housing tubes arranged in a circular pattern within a carousel, a set of frames, a cylindrical protective skin, an aerodynamically optimized nose cone with a bore, and an optional door covering the bore, enabling rockets or missiles to exit the launcher. The rotating launcher system may also include an aerodynamically optimized tail cone with a bore, and an optional door covering the bore, enabling exhaust from the rockets or missiles to exit the launcher. The rotating launcher system also includes an integral controller for an indexing motor, and an indexing motor enabling the bores of the nose and tail cones to align with different rockets or missiles in the carousel by either rotating the nose and tail cones, or by rotating the carousel.

Abstract: A method and computer graphics system for clip testing using clip bits stored in a general-purpose register for each vertex of a geometric primitive. In one embodiment, a rendering unit or other processor sets bits in a clip bits register for each vertex of a geometric primitive. Each bit indicates whether the vertex is inside or outside of a clipping boundary with respect to a particular clipping plane. A frame buffer controller or other graphics processor performs clip testing on the entire geometric primitive by performing Boolean operations on the clip bits. The frame buffer controller may trivially accept or trivially reject the primitive based on the clip testing. If the primitive cannot be trivially rejected or trivially accepted, then the frame buffer controller sends an interrupt to the rendering unit. The rendering unit reads an exception register to determine that the reason for the interrupt is the need to clip the primitive.

Abstract: A 3-D graphics accelerator for performing lighting operations using operands within a given fixed point numeric range. The 3-D graphics accelerator includes a first computational unit which is configured to compute a value of an attenuation factor usable for performing said lighting operation for local lights. The attenuation factor is represented in floating point format. The first computational unit is also configured to represent the attenuation factor in an intermediate format including a first intermediate value (a scaled attenuation factor value within the given fixed point numeric range), and a second intermediate value (a shift count usable to convert the scaled attenuation factor value back to the original attenuation factor value). The 3-D graphics accelerator further includes a lighting unit coupled to said first computational unit. The first computational unit is further configured to convey the intermediate representation of the attenuation factor to the lighting unit.

Abstract: A lighting unit for improved processing of multiple light sources. The lighting unit includes an input buffer for receiving one or more attributes corresponding to a given polygon. The lighting unit further includes a first light parameter storage location for storing a first set of light parameters for a first light source illuminating the given polygon, and a second light parameter storage location for storing a second set of light parameters for a second light source illuminating the given polygon. Still further, the lighting unit includes a first light type storage location which stores a lighting routine index for the first light source, and a second light type storage location which stores a lighting routine index for the second light source. The first light type storage location is initialized to be a current light type storage location. The lighting routine indices point to a particular lighting routine to be performed for a given type of light source.

Abstract: A computer system which exhibits increased performance for stereo viewing. The computer system includes a display screen, a bus for transferring data, a memory coupled to the bus for storing geometric primitives and left and right view transformation matrices. Furthermore, the computer system includes a processor coupled to the bus, wherein the processor is configured to enable stereo mode and to execute an application for rendering objects on the display screen in the stereo mode. The computer system also includes a graphics accelerator coupled to the bus. The graphics accelerator includes a buffer for storing a received geometric primitive to be rendered in stereo mode, as well as memory for storing the left and right view transformation matrices. The graphics accelerator also includes a transformation unit which is configured to generate a first transformed geometric primitive in response to the received geometric primitive and the left view transformation matrices.

Abstract: A lighting unit which exhibits improved handling of incoming color values corresponding to a polygon. The lighting unit includes an input buffer for storing a plurality of color values, a mode register including a color mode field specifying whether the plurality of color values corresponds to the front or back side of the polygon. Furthermore, the lighting unit includes a register file for storing color information. The register file includes a first and second plurality of registers for storing front and back side color information, respectively. Still further, the lighting unit includes input/output logic configured to perform a transfer color instruction, which first comprises accessing the mode register to obtain a value of the color mode field, and then transferring the plurality of color values from the input buffer to one or more registers within the register file.

Abstract: A floating point processor for a 3-D graphics accelerator which includes improved performance over prior art designs. The floating point processor includes three specialized engines or function units which streamline floating point operations and which provide improved performance over prior systems. In the preferred embodiment, the floating point processor comprises a floating point core (F-core), a lighting core (L-Core), and a set-up core (S-core). Computations for triangles and vectors are split over the three function units for improved efficiency. The F-core processor receives geometry primitive data and performs floating point operations on the received geometry data. The L-Core processor comprises a fixed point computational unit for performing lighting computations. The set-up core comprises a fixed point computational unit for performing set-up calculations for geometric primitives.