Abstract: A cooling system controller for a set of computing resources of a data center includes a first interface to couple to a first flow controller that controls a rate of thermal energy transfer to a PCM store from the set of computing resources, a second interface to couple to a second flow controller that controls a rate of thermal energy transfer from the PCM store to a cooling system, and a controller to determine a current set of operational parameters for the data center and to manipulate the first and second flow controllers and via the first and second interfaces to control a net thermal energy transfer to and from the PCM store based on the current set of parameters.

Abstract: A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

Abstract: A processing device includes a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A queue is used to convey data between the producing processor unit and the consuming processor unit. A system management unit is to modify one or both of an operating frequency or an operating voltage of one or both of the producing processor unit or the consuming processor unit based on a rate of change of a fullness of the queue.

Abstract: A heterogeneous processing device includes one or more relatively large processing units and one or more relatively small processing units. The heterogeneous processing device selectively activates a large processing unit or a small processing unit to run a process thread based on a predicted duration of an active state of the process thread.

Abstract: A mechanism is provided for a circuit for generation of a random output. A bistable circuit has two stable states as an output and a clock signal as an input. The bistable circuit includes a first logic circuit and a second logic circuit cross-coupled connected together, which transition into a metastable state before resolving to the two stable states. The second logic circuit resolves to a stable state at a resolution time. A digitization circuit is configured to generate random bits corresponding to a variance of the resolution time of the second logic circuit resolving from the metastable state to the stable state for cycles of the clock signal. The resolution time randomly varies according to noise. An actual value of the stable state is eliminated as factor in generating the random bits.

Abstract: A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

Abstract: A mechanism is provided for a circuit for generation of a random output. A bistable circuit has two stable states as an output and a clock signal as an input. The bistable circuit includes a first logic circuit and a second logic circuit cross-coupled connected together, which transition into a metastable state before resolving to the two stable states. The second logic circuit resolves to a stable state at a resolution time. A digitization circuit is configured to generate random bits corresponding to a variance of the resolution time of the second logic circuit resolving from the metastable state to the stable state for cycles of the clock signal. The resolution time randomly varies according to noise. An actual value of the stable state is eliminated as factor in generating the random bits.

Abstract: The present disclosure provides a method and a system for characterizing and identifying an electronic device using a physical fingerprint. In one aspect, the characterizing method includes determining the physical fingerprint of a test device using selected memory cells of an SRAM array in the test device, and storing data associated with the physical fingerprint in a database. The physical fingerprint of the test device includes data retention voltages respectfully corresponding to the selected memory cells. In one aspect, the identifying method includes characterizing a test device using data retention voltages of selected memory cells in the test device as a physical fingerprint of the test device, and comparing the physical fingerprint of the test device with a predetermined fingerprint of a target device.

Abstract: A digital processor has a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register.

Abstract: A digital processor has four components: a controller, a data converter, a data register, and a logarithmic calculator. The processor has an address bus and a data bus for communication therewith. The address bus is connected to the controller. The data bus is connected to the controller and to the data register. Program instructions from the data bus are supplied to the controller and data on the data bus are supplied to the data register. Program instructions supplied to the controller are decoded and internal program instructions are generated by the controller. The controller communicates with the data converter, data register, and the logarithmic calculator via an internal bus through the internal program instructions. Integer data from the data bus are stored in the data register. The data converter receives the integer data, converts it into logarithmic data, and stores it in the data register.

Abstract: A comparator array logic (CAL) circuit has a plurality of interconnected comparators arranged in an array. Each of the comparators stores a digital value. The CAL circuit stores all of the digital values in a monotonically increasing or decreasing order. Each of the comparators receives the input data signal and compares the input data signal to the digital value stored in the comparator. A comparison signal is generated in response to the comparison. The comparison signal from each comparator is received by an end cell which also receives the comparison signal from the immediately adjacent comparator. The end cell generates an output signal. An end cell is associated with each comparator. The plurality of output signals from the end cells represent the location of the comparator which borders the value of the input data signal.

Abstract: A calculating apparatus receives four operands ("a, b, c and d") simultaneously. A first multiplier/divider performs the calculation of a*b or a.div.b and provides an output u. A second multiplier/divider performs the calculation of c*d or c.div.d and provides an output v. An adder/subtractor receives u and v and performed the calculation of u+v and u-v. A controller controls the operation of the first and second multiplier/divider to select the operation of multiplication or division.

Abstract: A logarithmic converting apparatus for converting a digital binary integer into logarithmic representation and for converting logarithmic representation into digital binary integer is disclosed. The apparatus determines the bit position of a leading non-zero bit of an integer, shifts the integer such that the leading non-zero bit is the leftmost bit. A look-up table receives the shifted integer and provides a number representative of the mantissa portion of the logarithm of the shifted number. An encoder receives a Point Set Input value, a scale value for said integer, and the number of binary positions shifted and generates the exponential portion of the logarithm of the integer. For converting logarithmic representation of a number into integer representation, the apparatus has a look-up table which receives the mantissa component of the logarithmic representation and provides a first number.