Patents by Inventor Wayne Patrick Richling

Wayne Patrick Richling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7253528
    Abstract: A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by introducing an intermediate trace routing design between the current delivering trace and the pad that distributes the inflow of current from the trace to multiple points of entry on the pad. The intermediate trace routing design includes an outer trace channel connected to the current delivering trace. A plurality of conductive trace leads connect the outer trace channel to the pad. Preferably, each of the plurality of conductive trace leads is characterized by a respective trace impedance so as to distribute equal current flow through each of the leads to the pad.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: August 7, 2007
    Assignee: Avago Technologies General IP Pte. Ltd.
    Inventors: Walter John Dauksher, Wayne Patrick Richling, William S. Graupp
  • Patent number: 7208843
    Abstract: A novel pad structure for an integrated circuit component that utilizes a bump interconnect for connection to other integrated circuit components that produces a relatively uniform current distribution within the bump of the bump interconnect is presented. The pad structure includes an inner pad implemented on an inner conductive layer of the integrated circuit component, an outer pad implemented on an outer conductive layer of the integrated circuit component, and a plurality of vias connecting the inner pad and outer pad. The outer pad is sealed preferably around its edges with a passivation layer, which includes an opening exposing a portion of the outer pad. The vias connecting the inner pad and outer pad are preferably implemented to lie in a via region within the footprint of the pad opening.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: April 24, 2007
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Wayne Patrick Richling, Walter John Dauksher, William S. Graupp