Patents by Inventor Wayne R. Burger
Wayne R. Burger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9871008Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.Type: GrantFiled: November 4, 2016Date of Patent: January 16, 2018Assignee: NXP USA, INC.Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren
-
Publication number: 20170077051Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.Type: ApplicationFiled: November 4, 2016Publication date: March 16, 2017Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren
-
Patent number: 9520367Abstract: A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.Type: GrantFiled: August 20, 2014Date of Patent: December 13, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Zihao M. Gao, David C. Burdeaux, Wayne R. Burger, Robert A. Pryor, Philippe Renaud
-
Patent number: 9508599Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.Type: GrantFiled: April 22, 2015Date of Patent: November 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren
-
Publication number: 20160056114Abstract: A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.Type: ApplicationFiled: August 20, 2014Publication date: February 25, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Zihao M. Gao, David C. Burdeaux, Wayne R. Burger, Robert A. Pryor, Philippe Renaud
-
Publication number: 20150228545Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.Type: ApplicationFiled: April 22, 2015Publication date: August 13, 2015Inventors: PAUL W. SANDERS, WAYNE R. BURGER, THUY B. DAO, JOEL E. KEYS, MICHAEL F. PETRAS, ROBERT A. PRYOR, XIAOWEI REN
-
Patent number: 9064712Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44?, 45?) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1?, 52-1?, 94, 94?, 94?) overlying the substrate (60). The active transistor(s) (41?) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42?, 43?) are also formed over the front face (63) of the substrate (60). Various terminals (42-1?, 42-2?, 43-1, 43-2?,50?, 51?, 52?, 42-1?, 42-2?, etc.) of the transistor(s) (41?), capacitor(s) (42?, 43?) and inductor(s) (44?, 45?) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98?) to minimize parasitic resistance.Type: GrantFiled: August 12, 2010Date of Patent: June 23, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren
-
Patent number: 8906773Abstract: Embodiments of integrated passive devices (e.g., metal insulator metal, or MIM, capacitors) and methods of their formation include depositing a composite electrode over a semiconductor substrate (e.g., on a dielectric layer above the substrate surface), and depositing an insulator layer over the composite electrode. The composite electrode includes an underlying electrode and an overlying electrode deposited on a top surface of the underlying electrode. The underlying electrode is formed from a first conductive material (e.g., AlCuW), and the overlying electrode is formed from a second, different conductive material (e.g., AlCu). The top surface of the underlying electrode may have a relatively rough surface morphology, and the top surface of the overlying electrode may have a relatively smooth surface morphology. For high frequency, high power applications, both the composite electrode and the insulator layer may be thicker than in some conventional integrated passive devices.Type: GrantFiled: December 12, 2012Date of Patent: December 9, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Xiaowei Ren, Wayne R. Burger
-
Publication number: 20140159198Abstract: Embodiments of integrated passive devices (e.g., metal insulator metal, or MIM, capacitors) and methods of their formation include depositing a composite electrode over a semiconductor substrate (e.g., on a dielectric layer above the substrate surface), and depositing an insulator layer over the composite electrode. The composite electrode includes an underlying electrode and an overlying electrode deposited on a top surface of the underlying electrode. The underlying electrode is formed from a first conductive material (e.g., AlCuW), and the overlying electrode is formed from a second, different conductive material (e.g., AlCu). The top surface of the underlying electrode may have a relatively rough surface morphology, and the top surface of the overlying electrode may have a relatively smooth surface morphology. For high frequency, high power applications, both the composite electrode and the insulator layer may be thicker than in some conventional integrated passive devices.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Inventors: XIAOWEI REN, WAYNE R. BURGER
-
Patent number: 8283748Abstract: Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.Type: GrantFiled: October 20, 2011Date of Patent: October 9, 2012Assignee: Freescale Semiconductors, Inc.Inventors: Xiaowei Ren, Wayne R. Burger, Colin Kerr, Mark A. Bennett
-
Patent number: 8134241Abstract: Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.Type: GrantFiled: July 8, 2011Date of Patent: March 13, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Jeffrey K. Jones, Margaret A. Szymanowski, Michele L. Miera, Xiaowei Ren, Wayne R. Burger, Mark A. Bennett, Colin Kerr
-
Publication number: 20120037969Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44?, 45?) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1?, 52-1?, 94, 94?, 94?) overlying the substrate (60). The active transistor(s) (41?) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42?, 43?) are also formed over the front face (63) of the substrate (60). Various terminals (42-1?, 42-2?, 43-1, 43-2?,50?, 51?, 52?, 42-1?, 42-2?, etc.) of the transistor(s) (41?), capacitor(s) (42?, 43?) and inductor(s) (44?, 45?) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98?) to minimize parasitic resistance.Type: ApplicationFiled: August 12, 2010Publication date: February 16, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren
-
Publication number: 20120038023Abstract: Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.Type: ApplicationFiled: October 20, 2011Publication date: February 16, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xiaowei Ren, Wayne R. Burger, Colin Kerr, Mark A. Bennett
-
Patent number: 8071461Abstract: Electronic elements (44, 44?, 44?) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62?, 62?) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36?) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65?, 65?) in the composite dielectric region (62, 62?, 62?) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78?, 78?) in the composite dielectric region (62, 62?, 62?). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65?, 65?) and silicon oxide for the dielectric material (78, 78?, 78?).Type: GrantFiled: December 4, 2008Date of Patent: December 6, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Xiaowei Ren, Wayne R. Burger, Colin Kerr, Mark A. Bennett
-
Publication number: 20110266687Abstract: Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jeffrey K. Jones, Margaret A. Szymanowski, Michele L. Miera, Xiaowei Ren, Wayne R. Burger, Mark A. Bennett, Colin Kerr
-
Patent number: 7998852Abstract: Electronic elements (44, 44?, 44?) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44?, 44?) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36?) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62?, 62?) having electrically isolated inclusions (65, 65?, 65?) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78?, 78?) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65?, 65?) and silicon oxide for the dielectric material (78, 78?, 78?).Type: GrantFiled: December 4, 2008Date of Patent: August 16, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Jeffrey K. Jones, Margaret A. Szymanowski, Michele L. Miera, Xiaowei Ren, Wayne R. Burger, Mark A. Bennett, Colin Kerr
-
Publication number: 20100140714Abstract: Electronic elements (44, 44?, 44?) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62?, 62?) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36?) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65?, 65?) in the composite dielectric region (62, 62?, 62?) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78?, 78?) in the composite dielectric region (62, 62?, 62?). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65?, 65?) and silicon oxide for the dielectric material (78, 78?, 78?).Type: ApplicationFiled: December 4, 2008Publication date: June 10, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Xiaowei Ren, Wayne R. Burger, Colin Kerr, Mark A. Bennett
-
Publication number: 20100140814Abstract: Electronic elements (44, 44?, 44?) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44?, 44?) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36?) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62?, 62?) having electrically isolated inclusions (65, 65?, 65?) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78?, 78?) in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65?, 65?) and silicon oxide for the dielectric material (78, 78?, 78?).Type: ApplicationFiled: December 4, 2008Publication date: June 10, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jeffrey K. Jones, Margaret A. Szymanowski, Michele L. Miera, Xiaowei Ren, Wayne R. Burger, Mark A. Bennett, Colin Kerr
-
Patent number: 7525152Abstract: An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal including of one or more branch (54-1, 54-2, 116-1, 116-2, 116-11, 116-21, 116-41) of metal having a metal width maintained within a bamboo regime.Type: GrantFiled: February 23, 2007Date of Patent: April 28, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Christopher P. Dragon, Wayne R. Burger, Robert A. Pryor
-
Publication number: 20070205506Abstract: An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal including of one or more branch (54-1, 54-2, 116-1, 116-2, 116-11, 116-21, 116-41) of metal having a metal width maintained within a bamboo regime.Type: ApplicationFiled: February 23, 2007Publication date: September 6, 2007Inventors: Christopher P. Dragon, Wayne R. Burger, Robert A. Pryor