Abstract: A method and system for transporting traffic in a packet-switched network segments high priority pass-through traffic from low priority pass-through traffic. The high priority pass-through traffic is transmitted on an egress link preferentially over the low priority pass-through traffic and ingress high priority local traffic. The ingress high priority local traffic is transmitted on the egress link preferentially over the low priority pass-through traffic.

Abstract: A multiple time domain serial-to-parallel converter includes a combiner operable to receive a stream of serial data within a first time domain and to accumulate a portion of the serial data into a set of parallel data. A first hold register is coupled to the combiner. The first hold register is configured to operate within the first time domain and operable to load the set of parallel data in response to a first load signal based on the first time domain. A second hold register is coupled to the first hold register. The second hold register is configured to operate within a second time domain and operable to load the set of parallel data from the first hold register in response to a second load signal based on the second time domain.

Abstract: A method of simulating AC timing characteristics at the pins of a device in of an application specific integrated circuit (ASIC) design is presented. The approach is fully automatic and is generalized, in the sense that both positive and negative Setup and Hold times and Propagation delays can be captured. The approach allows each bit of a data bus to be treated individually so as to be able to identify the worst case Setup time, Hold time and Propagation delay. Measurement is carried out in parallel for all data inputs and outputs. The need for manual intervention is eliminated and considerably reduces simulation time. Delay files are used through a call from a test bench, and the same testbench can be run on different delay information, namely pre-layout or post-layout delays.