Abstract: A method of milling substantially insoluble solid organic biocides to form a micron or sub-micron product having a narrow particle size distribution is presented. The milling involves wet milling of the organic biocide with high density milling media having a diameter between 0.1 mm and 0.8 mm, preferably between 0.2 mm and 0.7 mm, and a density equal to or greater than 3.8 g/cc, preferably greater than 5.5 g/cc, in a ball mill using between about 40% and 80% loading of the mill volume with milling media, and having the organic biocide suspended in an aqueous milling liquid which comprises one or more surface active agents. The milling speed is preferably high, for example from about 1000 rpm to about 4000 rpm.

Abstract: A wood preservative includes injectable particles comprising one or more sparingly soluble copper salts. The copper-based particles are sufficiently insoluble so as to not be easily removed by leaching but are sufficiently soluble to exhibit toxicity to primary organisms primarily responsible for the decay of the wood. Exemplary particles contain for example copper hydroxide, basic copper carbonate, copper carbonate, basic copper sulfates including particularly tribasic copper sulfate, basic copper nitrates, copper oxychlorides, copper borates, basic copper borates, and mixtures thereof. The particles typically have a size distribution in which at least 50% of particles have a diameter smaller than 0.25 ?m, 0.2 ?m, or 0.15 ?m. At least about 20% and even more than 75% of the weight of the particles may be composed of the substantially crystalline copper salt. Wood or a wood product may be impregnated with copper-based particles of the invention.

Abstract: The invention includes a step device for assisting entry into and/or exit from a vehicle such as, for example, high road clearance truck. The step device comprises a generally “W” shaped bar which is separable into said two generally “U” shaped elements for easier packaging, shipping and manipulation of the device. Each of the “U” shaped elements include a cross-bar fixedly attached between, and spanning across, an interior of the generally “U” shaped element. The cross-bars are configured for separately mounting to the vehicle such that the generally “U” shaped elements are independently supported and the generally “U” shaped elements may be adjustable to multiple angles with respect to said vehicle.

Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

Abstract: The invention includes a step device for assisting entry into and/or exit from a vehicle such as, for example, high road clearance truck. The step device comprises a generally “W” shaped bar which is separable into said two generally “U” shaped elements for easier packaging, shipping and manipulation of the device. Each of the “U” shaped elements include a cross-bar fixedly attached between, and spanning across, an interior of the generally “U” shaped element. The cross-bars are configured for separately mounting to the vehicle such that the generally “U” shaped elements are independently supported and the generally “U” shaped elements may be adjustable to multiple angles with respect to said vehicle.

Abstract: A method of milling substantially insoluble solid organic biocides to form a micron or sub-micron product having a narrow particle size distribution is presented. The milling involves wet milling of the organic biocide with high density milling media having a diameter between 0.1 mm and 0.8 mm, preferably between 0.2 mm and 0.7 mm, and a density equal to or greater than 3.8 g/cc, preferably greater than 5.5 g/cc, in a ball mill using between about 40% and 80% loading of the mill volume with milling media, and having the organic biocide suspended in an aqueous milling liquid which comprises one or more surface active agents. The milling speed is preferably high, for example from about 1000 rpm to about 4000 rpm.

Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

Abstract: A method of dissolving a copper mass includes contacting a copper mass with an oxidant such as air and an aqueous leach liquor containing monoethanolamine (“MEA”) and (HMEA)2CO3, wherein said leach liquor is produced by partially carbonating the MEA, and said leach liquor further contains between 1.9 g/L and 13.7 g/L of dissolved copper, forms a liquid product comprising between 100 and 130 g Cu/L in 48 hours or less.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.

Abstract: A multi-mode memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval is imposed between successive accesses to a given row of the storage cells. Data path circuitry is provided to transfer data between the plurality of storage banks and an external signal path during first and second modes of operation of the memory device. During the first mode of operation a first data item is transferred, in response to a first memory access request, during a first time interval that is not longer than the minimum time interval. During the second mode of operation a plurality of data items are transferred during the first time interval, in response to a plurality of memory access requests.

Abstract: A wood preservative that contains a copper salt complex and a precipitation inhibitor is provided. The wood preservative may contain copper carbonate, an alkanolamine such as monoethanolamine and precipitation inhibitor such as a phosphonate or ethylene diamine compound. Also provided is a method of using the wood preservative.

Abstract: The invention relates to a compatibilizing dispersant used in a slurry composition comprising a strongly cationic component and a strongly anionic component. More specifically, the invention relates to stable aqueous slurries comprising suspended particles of sparingly soluble salts, oxide, and/or hydroxides of copper and/or zinc. The slurry further comprises a quaternary amine compound present in a biocidally effective amount when the slurry is used in a manner that provides the sparingly soluble copper and/or zinc containing particles in a biocidally effective amount. The slurry further comprises an effective amount of a dispersant having a large non-ionic component.

Abstract: Spent, acidic solutions comprising cupric chloride and hyrdrochloric acid from the copper etching process are regenerated by a process in which the acid is subjected to distillation with sulfuric acid. In one embodiment, the process comprises (a) providing a spent etchant comprising at least about 10% by weight chloride and at least about 5% dissolved copper; (b) adding at least about 2 moles of sulfuric acid per mole of dissolved copper to the spent etching solution, thereby converting copper chloride into hydrochloric acid and precipitated copper sulfate; (c) distilling the mixture from step (b) to vaporize at least a portion of the hydrochloric acid; (d) condensing at least a portion of the vaporized hydrochloric acid; (e) separating at least a portion of the precipitated copper sulfate from the residual liquid, wherein said residual liquid comprises sulfuric acid; and (f) reusing at least a portion of the residual liquid as a sulfuric acid source in step (b).

Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device comprises an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation.

Abstract: A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.