Abstract: A microprocessor-based system includes a central processing unit (CPU) and a CPU memory coupled by a CPU bus. A DMA sampler is coupled to the CPU, the CPU memory and the CPU bus. The DMA sampler includes sampling circuitry which is implemented as a finite state machine to maintain a substantially exact sampling rate on at least one analog input signal provided to the DMA sampler. The DMA sampler also includes DMA circuitry implemented as a data flow machine, which requests bus mastership from the CPU when samples obtained by the DMA sampler are available for transfer to the CPU memory. In response to the request, the CPU relinquishes bus mastership to the DMA sampler which provides the sample to the CPU memory and returns bus mastership to the CPU.