Abstract: Techniques regarding forming flip chip interconnects are provided. For example, one or more embodiments described herein can comprise a three-dimensionally printed flip chip interconnect that includes an electrically conductive ink material that is compatible with a three-dimensional printing technology. The three-dimensionally printed flip chip interconnect can be located on a metal surface of a semiconductor chip.

Abstract: One embodiment of an integrated circuit includes a substrate, an electrical device positioned above the substrate, and a bond bad positioned above and aligned along a vertical axis with the electrical device such that the electrical device is positioned between the substrate and the bond pad.

Abstract: A single-pole multiple-throw RF switch includes first and second FET arrangements, each having a gate and a controlled current path (CCP). One end of the CCP of each FET is connected to a common port by way of an arrangement which blocks DC flow between the FETs, but allows RF flow. Bias is applied to the gates of the FETs to enable RF flow through the CCP of a selected one and not through the others. One version uses a single bias source and cross-coupled resistors, and another version uses plural bias sources switched to the various FETs.

Abstract: Decoder logic for an RF switch includes first and second enhancement mode transistors and a depletion mode transistor. Sources of the depletion mode transistor and the first enhancement mode transistor are coupled to a VDD supply. The drain and gate of the depletion mode transistor are coupled to the gate of the first enhancement mode transistor. The second enhancement mode transistor is coupled between ground and the drain of the depletion mode transistor. In active mode, the second enhancement mode transistor is turned off and the depletion mode transistor applies a high voltage to the gate of the first enhancement mode transistor, thereby turning on the first enhancement mode transistor to couple the RF switch the VDD supply. In inactive mode, the second enhancement mode transistor is turned on, thereby turning off the first enhancement mode transistor and providing a low current path between the VDD supply terminal and ground.

Abstract: An integrated circuit package houses and connects to a die to form an integrated circuit with internal matching. The package comprises a lead frame comprising at least one transmission line, a die paddle, and at least one input lead and at least one output lead. Bond wires connect select locations along the at least one transmission line to ground through impedance matching circuit components located within the integrated circuit to provide an impedance matching network associated with at least one of the output leads. A plastic mold compound substantially encases the lead frame, while exposing the die paddle and the input/output leads. Incorporating the transmission line into the lead-frame avoids having to place the matching network outside of the integrated circuit package. That is, etching the lead frame to provide the transmission line, and placing components (e.g., capacitors, inductors, etc.

Abstract: A single-pole multiple-throw RF switch includes first and second FET arrangements, each having a gate and a controlled current path (CCP). One end of the CCP of each FET is connected to a common port by way of an arrangement which blocks DC flow between the FETs, but allows RF flow. Bias is applied to the gates of the FETs to enable RF flow through the CCP of a selected one and not through the others. One version uses a single bias source and cross-coupled resistors, and another version uses plural bias sources switched to the various FETs.

Abstract: An integrated circuit package houses and connects to a die to form an integrated circuit with internal matching. The package comprises a lead frame comprising at least one transmission line, a die paddle, and at least one input lead and at least one output lead. Bond wires connect select locations along the at least one transmission line to ground through impedance matching circuit components located within the integrated circuit to provide an impedance matching network associated with at least one of the output leads. A plastic mold compound substantially encases the lead frame, while exposing the die paddle and the input/output leads. Incorporating the transmission line into the lead-frame avoids having to place the matching network outside of the integrated circuit package. That is, etching the lead frame to provide the transmission line, and placing components (e.g., capacitors, inductors, etc.