Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

Abstract: An integrated electrostatic discharge (ESD) device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD structure coupled to a ground terminal of the integrated ESD device. The integrated ESD device also comprises a diffusion region that is shared by each of the first ESD structure and the second ESD structure, such that the shared diffusion region forms a portion of at least one semiconductor junction associated with each of the first ESD structure and the second ESD structure.

Abstract: An integrated electrostatic discharge (ESD) device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD structure coupled to a ground terminal of the integrated ESD device. The integrated ESD device also comprises a diffusion region that is shared by each of the first ESD structure and the second ESD structure, such that the shared diffusion region forms a portion of at least one semiconductor junction associated with each of the first ESD structure and the second ESD structure.

Abstract: A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver includes a voltage divider network connected to a front-end amplifier for dividing down the input signal from a two wire line by a predetermined amount and amplifying the signal by the same predetermined amount. The front-end amplifier generates the common-mode voltage of the input signal for a reference generator that determines the logic level of the incoming signal and subtracts a bandgap voltage reference from the common-mode voltage. A comparator compares the difference between the output of the front-end amplifier and the resultant signal generated by the reference generator to generate an output signal for the receiver. This CAN receiver architecture is faster than conventional designs and possesses an improved common-mode rejection, while operating over a wide input common mode range.

Abstract: An integrated electrostatic discharge (ESD) device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD structure coupled to a ground terminal of the integrated ESD device. The integrated ESD device also comprises a diffusion region that is shared by each of the first ESD structure and the second ESD structure, such that the shared diffusion region forms a portion of at least one semiconductor junction associated with each of the first ESD structure and the second ESD structure.

Abstract: A differential bus network, in general, or a controller area network (CAN) driver, in particular, controls and minimizes the variation on the common-mode signal of the CAN bus. This CAN driver also provides improved symmetry between its differential output signals, CANH and CANL, and provides protection for its low voltage devices from voltage transients occurring on its output lines. The common-mode signal is sensed and buffered, then during the dominant to recessive transition, the bus signals are shorted to the buffered common mode voltage. Specifically, additional switches or transistors are used to pull the differential output signals, CANH and CANL, to the common mode signal VCM when the state of the CAN bus transitions from dominant to recessive. This improvement minimizes high frequency spikes in the common-mode signal and eliminates DC shifts during transitions of the state of the CAN bus.

Abstract: System and method for controlling current across a load. A preferred embodiment comprises a current varying circuit (such as current varying circuit 525) that can create a sequence of voltage drops in a driver circuit (such as the driver circuit 505) coupled to an inductive load (such as the inductive load 535). By initially producing a large voltage drop and then stepping the voltage drop down gradually, the current in the inductive load can be rapidly removed without producing a current undershoot, which, in certain applications, can result in unwanted noise and vibration.

Abstract: System and method for controlling current across a load. A preferred embodiment comprises a current varying circuit (such as current varying circuit 525) that can create a sequence of voltage drops in a driver circuit (such as the driver circuit 505) coupled to an inductive load (such as the inductive load 535). By initially producing a large voltage drop and then stepping the voltage drop down gradually, the current in the inductive load can be rapidly removed without producing a current undershoot, which, in certain applications, can result in unwanted noise and vibration.

Abstract: A modulation scheme can drive an associated load that is coupled between a pair of outputs by providing a switching signal at one of the outputs and a non-switching signal at the other output independent of the direction of current relative to the respective outputs. Because switching occurs only at one of the outputs in this mode of operation, a single filter can be used to mitigate switching noise at the switching output. Another aspect relates to another mode of operation in which one or both of the outputs can be controlled to operate linearly, such as during a zero crossing condition, so as to help reduce crossover distortion.

Abstract: A modulation scheme can drive an associated load that is coupled between a pair of outputs by providing a switching signal at one of the outputs and a non-switching signal at the other output independent of the direction of current relative to the respective outputs. Because switching occurs only at one of the outputs in this mode of operation, a single filter can be used to mitigate switching noise at the switching output. Another aspect relates to another mode of operation in which one or both of the outputs can be controlled to operate linearly, such as during a zero crossing condition, so as to help reduce crossover distortion.

Abstract: A high voltage output stage amplifier that maximizes the output voltage swing when the peak-to-peak output voltage signal is higher than the supply voltage used in the signal conditioning circuits of the amplifier. The amplifier allows the maximum peak-to-peak swing on the output stage by shifting the quiescent voltage of the output stage to the midpoint of the output supply voltage. The shift is accomplished by tapping an offset current at the input of the error integrating stage of the amplifier proportional to the difference in the two power supply voltages.

Abstract: A Class-D switching amplifier (30, 40) having a ternary mode of operation. Signal processing (21, 22) is provided to eliminate the potential of crosstalk within one channel by introducing a time delay into the system. A susceptible crosstalk point is moved away from a zero-crossing point to a higher power level, which is advantageous in low-end audio applications. A time delay is introduced to one ramp signal (RAMPB) in the first implementation (30), and an in-sync generator (42) is utilized in another implementation (40) using offset switching in the comparitors (40, 42) to create the time delay (&Dgr;t).

Abstract: A Class-D switching amplifier (20) having a terinary modulation scheme implemented in an H-bridge configuration. The present invention has four states of operation, and achieves increased efficiency and reduced cost by delivering current to the load only when needed, and once delivered, maintaining the current. The Class-D switching amplifier eliminates the need for post amplifier filters.