Patents by Inventor Wayne Tseng
Wayne Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8234530Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.Type: GrantFiled: May 18, 2011Date of Patent: July 31, 2012Assignee: Via Technologies Inc.Inventor: Wayne Tseng
-
Patent number: 8051350Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.Type: GrantFiled: December 30, 2008Date of Patent: November 1, 2011Assignee: Via Technologies Inc.Inventor: Wayne Tseng
-
Publication number: 20110225470Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.Type: ApplicationFiled: May 18, 2011Publication date: September 15, 2011Applicant: VIA TECHNOLOGIES INC.Inventor: Wayne Tseng
-
Patent number: 7640383Abstract: A method and related apparatus for different lane and access port configurations of a bus. Such different configurations can apply to different applications requirements. In a preferred embodiment of the invention, a chipset can configure 18 lanes to 4 access ports of a peripheral communication interconnect express bus for selectively 4 different configurations. A first configuration provides single access port with 16 lanes, and two access ports for each has one lane. A second configuration provides two access ports for each has eight lanes, and two access ports for each has single lane. A third configuration provides one access port with eight lanes, two access ports for each has four lanes and another one access port with single lane. And a fourth configuration provides four access ports for each has four lanes.Type: GrantFiled: August 26, 2005Date of Patent: December 29, 2009Assignee: VIA Technologies Inc.Inventor: Wayne Tseng
-
Patent number: 7613959Abstract: A data receiving apparatus of a PCI Express system includes a receiving device, an 8B10B decoder, a forged packet removing device, and a descrambling circuit. The forged packet removing device determines whether a disparity error occurs; and an offset removing circuit compensates a number of cycles of the lane offset. The data receiving apparatus is capable of eliminating error packet caused by framing error and preventing the problem of symbol disorder and disconnection caused by set ordered noise. Furthermore, the data receiving apparatus is also capable of removing offset.Type: GrantFiled: August 30, 2005Date of Patent: November 3, 2009Assignee: VIA Technologies Inc.Inventor: Wayne Tseng
-
Publication number: 20090119053Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.Type: ApplicationFiled: December 30, 2008Publication date: May 7, 2009Inventor: Wayne Tseng
-
Patent number: 7490278Abstract: A built-in self test circuit includes a first pattern generator, an elastic buffer receiver, a command symbol detector, a second pattern generator, and a logic unit. The architecture is capable of compensating loopback latency automatically without having to utilize a device that stores test patterns generated by the first pattern generator, and error warning can be greatly reduced. Also, the architecture can reduce the effect of phase jitter and error rate count is provided. Hence, accuracy of test can be increased.Type: GrantFiled: August 30, 2005Date of Patent: February 10, 2009Assignee: VIA Technologies Inc.Inventor: Wayne Tseng
-
Patent number: 7441128Abstract: In a power management method of a computer system, the CPU asserts a clock-suspending grant cycle in response to a clock-suspending signal issued by the south bridge chip, and the south bridge chip issues the clock-suspending signal in response to a data write cycle asserted by the CPU. The clock-suspending grant cycle is to be transmitted to the south bridge chip via the north bridge chip when the CPU is ready to enter a power-saving mode. The north bridge chip performs a first power management operation of the peripheral device in response to the clock-suspending grant cycle. The south bridge chip performs a second power management operation of the computer system in response to the clock-suspending grant cycle.Type: GrantFiled: August 4, 2005Date of Patent: October 21, 2008Assignee: Via Technologies, Inc.Inventors: Tony Ho, Wayne Tseng
-
Patent number: 7346798Abstract: A circuit and a method for aligning transmitted data by adjusting transmission timing for a plurality of lanes. The method includes utilizing different initial values to reset a count value corresponding to a lane when a plurality of COM symbols are detected on the lane, utilizing an increment value to increase the count value corresponding to the lane when a COM symbol is not detected on the lane, and utilizing a plurality of count values corresponding to the lanes to align transmitted data of the lanes when a COM symbol is not detected on the lanes within a predetermined period of time.Type: GrantFiled: January 17, 2007Date of Patent: March 18, 2008Assignee: VIA Technologies Inc.Inventor: Wayne Tseng
-
Patent number: 7231560Abstract: This invention discloses a method for testing at least one physical link on a motherboard associated with an on-board PCI Express device. A test card is connected to an input/output port on the motherboard, wherein the test card has a PCI Express test device. A test pattern is transmitted from the test card to the PCI Express device and receiving a test result pattern by the test card from the PCI Express device through the physical link for testing thereof. The test result pattern is examined to determine defects of the physical link on the motherboard.Type: GrantFiled: November 10, 2004Date of Patent: June 12, 2007Assignee: Via Technologies, Inc.Inventors: Jiin Lai, Wayne Tseng
-
Publication number: 20070124623Abstract: A circuit and a method for aligning data transmitting timing of a plurality of lanes. The method includes utilizing different initial values to reset a count value corresponding to a lane when a plurality of COM symbols are detected on the lane, utilizing an increment value to increase the count value corresponding to the lane when a COM symbol is not detected on the lane, and utilizing a plurality of count values corresponding to the lanes to align data transmitting timing of the lanes when a COM symbol is not detected on the lanes within a predetermined period of time.Type: ApplicationFiled: January 17, 2007Publication date: May 31, 2007Inventor: Wayne Tseng
-
Patent number: 7225354Abstract: A circuit and a method for aligning transmitted data by adjusting transmission timing for a plurality of lanes. The method includes utilizing different initial values to reset a count value corresponding to a lane when a plurality of COM symbols are detected on the lane, utilizing an increment value to increase the count value corresponding to the lane when a COM symbol is not detected on the lane, and utilizing a plurality of count values corresponding to the lanes to align transmitted data of the lanes when a COM symbol is not detected on the lanes within a predetermined period of time.Type: GrantFiled: June 30, 2004Date of Patent: May 29, 2007Assignee: VIA Technologies Inc.Inventor: Wayne Tseng
-
Patent number: 7082501Abstract: A DSM system includes a local node, a first remote node, and a second remote nodes. The data access method for a remote node to access a local node in the DSM system includes the steps of directly receiving data of a local memory line from a local memory of the local node, and transmitting the data to the first remote node when the local memory line is in HOME-N or SHARED status; directly receiving data of the local memory line from the second remote node, and transmitting the data to the first remote node when the local memory line is in a GONE status; and asserting a transaction to a system bus to read data of the local memory line, receiving the data via the system bus, and transmitting the data to the first remote node when the local memory line is in HOME-M status.Type: GrantFiled: April 2, 2003Date of Patent: July 25, 2006Assignee: Via Technologies, Inc.Inventors: Wei-Long Chen, Jiin Lai, Wayne Tseng
-
Publication number: 20060123298Abstract: A built-in self test circuit includes a first pattern generator, an elastic buffer receiver, a command symbol detector, a second pattern generator, and a logic unit. The architecture is capable of compensating loopback latency automatically without having to utilize a device that stores test patterns generated by the first pattern generator, and error warning can be greatly reduced. Also, the architecture can reduce the effect of phase jitter and error rate count is provided. Hence, accuracy of test can be increased.Type: ApplicationFiled: August 30, 2005Publication date: June 8, 2006Inventor: Wayne Tseng
-
Publication number: 20060117125Abstract: A data receiving apparatus of a PCI Express system includes a receiving device, an 8B10B decoder, a forged packet removing device, and a descrambling circuit. The forged packet removing device determines whether a disparity error occurs; and an offset removing circuit compensates a number of cycles of the lane offset. The data receiving apparatus is capable of eliminating error packet caused by framing error and preventing the problem of symbol disorder and disconnection caused by set ordered noise. Furthermore, the data receiving apparatus is also capable of removing offset.Type: ApplicationFiled: August 30, 2005Publication date: June 1, 2006Inventor: Wayne Tseng
-
Publication number: 20060112210Abstract: A method and related apparatus for different lane and access port configurations of a bus. Such different configurations can apply to different applications requirements. In a preferred embodiment of the invention, a chipset can configure 18 lanes to 4 access ports of a peripheral communication interconnect express bus for selectively 4 different configurations. A first configuration provides single access port with 16 lanes, and two access ports for each has one lane. A second configuration provides two access ports for each has eight lanes, and two access ports for each has single lane. A third configuration provides one access port with eight lanes, two access ports for each has four lanes and another one access port with single lane. And a fourth configuration provides four access ports for each has four lanes.Type: ApplicationFiled: August 26, 2005Publication date: May 25, 2006Inventor: Wayne Tseng
-
Publication number: 20060047984Abstract: In a power management method of a computer system, the CPU asserts a clock-suspending grant cycle in response to a clock-suspending signal issued by the south bridge chip, and the south bridge chip issues the clock-suspending signal in response to a data write cycle asserted by the CPU. The clock-suspending grant cycle is to be transmitted to the south bridge chip via the north bridge chip when the CPU is ready to enter a power-saving mode. The north bridge chip performs a first power management operation of the peripheral device in response to the clock-suspending grant cycle. The south bridge chip performs a second power management operation of the computer system in response to the clock-suspending grant cycle.Type: ApplicationFiled: August 4, 2005Publication date: March 2, 2006Inventors: Tony Ho, Wayne Tseng
-
Publication number: 20050235187Abstract: This invention discloses a method for testing at least one physical link on a motherboard associated with an on-board PCI Express device. A test card is connected to an input/output port on the motherboard, wherein the test card has a PCI Express test device. A test pattern is transmitted from the test card to the PCI Express device and receiving a test result pattern by the test card from the PCI Express device through the physical link for testing thereof. The test result pattern is examined to determine defects of the physical link on the motherboard.Type: ApplicationFiled: November 10, 2004Publication date: October 20, 2005Inventors: Jiin Lai, Wayne Tseng
-
Patent number: 6931496Abstract: A distributed shared memory (DSM) system includes at least a first and a second nodes. The first node includes an external cache for storing a data from a local memory of the second node and at least two processors optionally accessing the data from the external cache. Whether the data has been modified into a modified data by a first certain one of the at least two processors is first determined. If positive, whether a second certain one of the at least two processors is allowed to share the modified data is further determined. If the second certain processor is allowed to share the modified data, it may directly request the modified data from the first certain processor via a bus inside the first node.Type: GrantFiled: April 9, 2003Date of Patent: August 16, 2005Assignee: Via Technologies, Inc.Inventors: Wei-Long Chen, Wayne Tseng, Jiin Lai
-
Publication number: 20050005051Abstract: A circuit and a method for aligning data transmitting timing of a plurality of lanes. The method includes utilizing different initial values to reset a count value corresponding to a lane when a plurality of COM symbols are detected on the lane, utilizing an increment value to increase the count value corresponding to the lane when a COM symbol is not detected on the lane, and utilizing a plurality of count values corresponding to the lanes to align data transmitting timing of the lanes when a COM symbol is not detected on the lanes within a predetermined period of time.Type: ApplicationFiled: June 30, 2004Publication date: January 6, 2005Inventor: Wayne Tseng