Abstract: A method and system in a data processing system for accessing information using an instruction specifying a memory address is disclosed. The method and system comprises issuing the instruction to an execution unit and storing an address derived from the specified address. The method and system also includes accessing a cache to obtain the information, using the derived address and determining, in response to a signal indicating that there has been a cache miss, if there is a location available to store the specified address in a queue. According to the system and method disclosed herein, the present invention allows for dynamic pipeline expansion of a processor without splitting this function between components depending upon the reason expansion was required, thereby increasing overall system performance.

Abstract: One aspect of the invention relates to a super scalar processor having a memory which as addressable with respect to the combination of a page address and a page offset address, and provides a method for detecting an overlap condition between a present instruction and a previously executed instruction, the previously executed instruction being executed prior to execution of the present instruction. In one embodiment, the method comprises the steps of dividing the present instruction into a plurality of aligned memory accesses; determining the page offset for at least one of the aligned accesses; and comparing the page offset and byte count for the present instruction to a page offset and byte count for the previously executed instruction.

Abstract: A system and method for reclaiming backing material from waste carpet or other products includes a chopper capable of handling large pieces of waste carpet, at least two grinding or granulation steps to reduce the size of the waste carpet pieces and to dislodge carpet fibers from the remaining material, and at least three separation steps to remove the dislodged fibers; one of the separation steps involves vibratory screening. Backing material reclaimed in this manner has a relatively low contamination level, and is suitable for reuse as carpet backing with little need for the addition of virgin backing material. The system and method further provide for the extrusion of the reclaimed backing material for use as new carpet backing.

Abstract: An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request.

Abstract: In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.

Abstract: To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.

Abstract: A vehicle headlight assembly includes a snapping engagement between a bezel, a housing and a lens. The snapping engagement positions all three pieces relative to each other during a manufacturing or assembly process. The light bulbs of the headlamp assembly are supported on the internally aimed reflector by bulb retainers that snappingly engage openings in the reflector. The bulbs preferably include housings that bias tab members on the bulb retainers into engagement with the reflector. The reflector is moved within the housing to direct the beam of light from the bulbs. Socket retainers snappingly engage the reflector. Ball members on conventional adjustors are received within the socket retainers so that the adjustors support the reflector within the housing and provide the ability to adjust the angular position of the bulbs and reflector relative to the remainder of the assembly.

Abstract: The write notification during copy system functions to enable the data processor to manage the data file copy function of a disk data storage subsystem in a manner that minimizes the expenditure of data processor resources. This is accomplished by the write notification during copy system determining the source volume on the data storage subsystem, the target volume on the data storage subsystem and identifying the extents of both. The write notification during copy system then transmits data to the data storage subsystem, representative of the assignment of DASD full tracks from the source location on the data storage subsystem as well as DASD full tracks from the target location on the data storage subsystem. The data processor based write notification during copy system then uses ECAM channel programs to instruct the data storage subsystem to perform the data file copy operation using snapshot track pointer copy operations.

Abstract: The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of assigning an identification tag to an instruction, and dispatching the instruction, the identification tag and source information to an execution queue.

Abstract: The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of dispatching the instruction and source information to a queue, determining validity of the source information, and issuing the instruction for execution in response to the source information validity.

Abstract: In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction.

Abstract: The invention includes a method and apparatus for maintaining content of predefined registers of a processor which uses the registers for executing instructions, including an interruptible instruction. According to the invention, instructions are dispatched, including instructions ("targeting instructions") which target registers for holding register content, and an interruptible instruction. The content of a register is altered in response to executing a targeting instruction. An entry of register content is stored only for selected ones of the dispatched targeting instructions.

Abstract: The present invention is directed to a method and apparatus for dispatching instructions in an information handling system. A pre-execution queue stores instructions, and at least one execution cluster is operably coupled to the pre-execution queue. An execution cluster comprises an early execution unit for executing a first instruction dispatched from the pre-execution queue to generate and forward a first result and a late execution unit for executing a second instruction dispatched from the pre-execution queue to generate and forward a second result after the first execution unit forwards the first result. The invention further includes circuitry operably associated with the pre-execution queue, and a method for prioritizing the order in which the instructions in the pre-execution queue are dispatched to the execution cluster.

Abstract: A method and apparatus for maintaining content of registers of a processor which uses the registers for processing instructions. Entries are stored in a buffer for restoring register content in response to an interruption by an interruptible instruction. Entries include information for reducing the number of entries selected for the restoring. A set of the buffer entries is selected, in response to the interruption and the information, for restoring register content. The set includes only entries which are necessary for restoring the content in response to the interruption so that the content of the processor registers may be restored in a single processor cycle, even if multiple entries are stored for a first one of the registers and multiple entries are stored for a second one of the registers.

Abstract: A data processor assigns a unique identifier to each instruction. As there are a finite number of unique identifiers, the identifiers are reused during execution of a program within the data processing system. To maintain an age relationship between instructions executing in the pipeline processor, a methodology is developed to ensure that reused identifiers are properly designated as being younger than their older but larger in magnitude, counterparts. To resolve this issue, assume that the identifier assigned to each instruction has N bits, and therefore, there are 2.sup.N identifiers to be assigned to instructions in the program. The 2.sup.N identifiers are separated into 2.sup.m banks. In addition to assigning identifiers to each instruction, an identifier assignment logic circuit within the pipeline processor provides a global signal that indicates which bank is a youngest bank from which the identifiers are assigned to a remaining portion of the pipeline processor.

Abstract: An age-based arbitration scheme for enforcing data coherency in an information handling system is disclosed. As loads and stores access a cache, if a cache miss occurs, a miss request is generated and tagged with the cycle or age in which the miss is detected. If a castout is required, it is also tagged with the cycle in which the load or store access occurred, and the line being replaced or cast out is marked as being invalid in that level of hierarchy. The arbitration rules for the next level of memory hierarchy are defined such that all requests that are generated during a particular cycle are given priority over all of the requests generated during any subsequent cycle. As a result, if a load miss occurs for a cache line which is present in the castout buffer, the castout request tagged with an earlier age will be arbitrated into the next memory hierarchy level prior to the arrival of the newly generated miss requests.

Abstract: A method and system are disclosed for reducing run-time delay during conditional branch instruction execution in a pipelined processor system. A series of queued sequential instructions and conditional branch instructions are processed wherein each conditional branch instruction specifies an associated conditional branch to be taken in response to a selected outcome of processing one or more sequential instructions. Upon detection of a conditional branch instruction within the queue, a group of target instructions are fetched based upon a prediction that an associated conditional branch will be taken. Sequential instructions within the queue following the conditional branch instruction are then purged and the target instructions loaded into the queue only in response to a successful a retrieval of the target instructions, such that the sequential instructions may be processed without delay if the prediction that the conditional branch is taken proves invalid prior to retrieval of the target instructions.

Abstract: An insulative housing has a first recess provided with a threaded metal insert adapted to engage a threaded antenna mount on a vehicle. A second relatively smaller recess through which an antenna whip extends has a compression spring which, when the antenna is installed on the vehicle, urges the contact at the lower end of the whip into secure electrical contact with the contact on the mount and also operates to compress a weather seal about the whip at the upper end of the recess.

Abstract: A low profile mobile antenna mounting of a simplified construction having a stamped sheet metal mounting bracket adapted for use with multiple size openings in the vehicle body.

Abstract: An electrical tap connector for making an electrical connection to an insulation covered cable at a point remote from the ends thereof. An insulative cable retaining body is provided with a conductive insulation piercing cable tap which extends from the body to form an electrical accessory lug.