Abstract: Reusable flow cells for sequencing which exhibit signal intensity retention over numerous use cycles, the active surface of which contains poly-azide functional moieties, methods of treating flow cells surfaces with reagents to provide such poly-azide functional moieties, and reagents therefor.

Abstract: Devices and methods for determining the cumulative distribution of a polymer property in a reactor without physical separation of reaction subcomponents. The device includes a means of measuring an instantaneous property of the polymers being produced in a reaction vessel a plurality of times during a polymerization reaction as well as a means of determining the corresponding change in polymer concentration in the reaction vessel between measurements of the instantaneous polymer property. The device also includes a means of computing a statistical distribution appropriate to the polymer characteristic and applying the statistical distribution to a recently measured instantaneous value of the polymer property so as to have an instantaneous distribution of the polymer property and a means of adding together the instantaneous distributions of the polymer property in order to obtain the cumulative distribution of the polymer property in the reactor.

Abstract: A bus interface control system and method includes an on-demand bus master interface for independently requesting multistream data from host memory without interrupting processing of the host processor between independent requests for data packets. A plurality of digital signal processors share the host bus and utilize flexible data speed transfer depending upon demand of real time data that must be transferred from host memory. The master interface control system includes an packet by packet arbitor to facilitate maximum throughput of data on-demand by the plurality of processing unit.

Abstract: A universal asynchronous receiver transmitter (UART) emulation stage for modem communication uses a digital signal processor containing a software UART control program for sending UART control signals to hardware based UART emulation circuitry. The software UART control program communicates to a modem application interface program that is under control of a host processor. The UART emulation circuitry that is responsive to the control signals from the digital signal processor, includes dedicated transmit and receive FIFO buffer memory for storing modem data and also includes interrupt generation logic to generate an interrupt for the digital signal processor when the received FIFO buffer memory is at a predetermined threshold. The UART emulation circuitry also includes programmable control logic for facilitating host processor interrupt pacing to maintain high compatibility with legacy applications, namely DOS based applications.

Abstract: An audio bus interface system and method interfaces a plurality of digital signal processing devices to an audio bus to facilitate variable processing loading on the DSPs. The audio bus contains frames with synchronization data. The system utilizes a programmable interrupt controller for each digital signal processing unit. The programmable interrupt controller controls the rate at which a given DSP can be interrupted. The respective digital signal processor controls the programmable interrupt controller to maximize its throughput. Also, an audio format translator allows differing audio format protocols to be processed by the same audio DSP.

Abstract: A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. A channel module, which is disposed between a switch module and a plurality of fiber optic channels, comprises a port intelligence system and a memory interface system. The port intelligence system is responsible for transmitting and receiving data from the fiber optic channels in accordance with a predetermined protocol, preferably Fibre Channel. The memory interface system comprises a receive memory unit, a transmit memory unit and memory control logic. When an intermix frame is to be passed through the switch, the intermix frame is passed to the buffer concurrently while class 1 data transfer occurs via the bypass bus.

Abstract: A method and apparatus for high speed decoding of a 20 bit wide data into 16-bit wide data in which the first ten bits and the lower ten bits are decoded simultaneously to ensure complete decoding and where the decoding of the second ten bits is dependent upon the running disparity of the first ten bits, the second ten bits are decoded twice, one assuming the decoded first ten bits will have a positive running disparity, and a second time assuming that the decoded first ten bits will have a negative running disparity.

Abstract: A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a first-in-first-out (FIFO) buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. A channel module, which is disposed between a switch module and a plurality of fiber optic channels, comprises a port intelligence system and a memory interface system. The port intelligence system is responsible for transmitting and receiving data from the fiber optic channels in accordance with a predetermined protocol, preferably Fibre Channel. The memory interface system comprises a receive memory unit, a transmit memory unit and memory control logic. When an intermix frame is to be passed through the switch, the intermix frame is passed to a FIFO concurrently while class 1 data transfer occurs via the bypass bus.