Abstract: A programmable state machine of an application specific integrated circuit (ASIC) is programmed by enabling the scan mode of the integrated circuit. The process of programming the state machine continues by loading, through at least one scan chain to which the state machine is coupled, at least one timing sequence instruction into scan capable registers of the state machine. Once the at least one timing sequence instruction has been loaded into the scan capable registers, the scan mode is disabled and normal mode of the integrated circuit is resumed.

Abstract: A method or apparatus for error identification of a BCH encoded signal includes processing that begins by receiving a BCH encoded signal in a binary polynomial format to produce a received polynomial. The processing then continues by converting the received polynomial into a plurality of error identifying polynomials. The processing then continues by recursively processing the plurality of binary error identifying polynomials to produce a plurality of error identifying values. The processing then continues by processing the plurality of error identifying values to produce an error locator polynomial that represents error in the received polynomial. The processing then continues by evaluating the error locator polynomial to identify the bit location of the error in the BCH encoded signal. The processing then continues by correcting the BCH encoded signal based on the bit location of the error.

Abstract: A method or apparatus for decoding of a BCH encoded signal begins by determining whether the received BCH encoded signal includes error. The decoding process continues when the received BCH encoded signal includes error by determining whether the error is correctable. This may be done by determining a number of errors of the received BCH encoded signal, identifying bit locations of the received BCH encoded signal having the error; counting the number of bit locations of the received BCH encoded signal having the error, comparing the number of errors to the number of bit locations of the received BCH encoded signal having the error, when the number of bit locations of the received BCH encoded signal having the error equals the number of errors, ceasing the identifying of the bit locations of the received BCH encoded signal having the error, and correcting information contained in the bit locations of the received BCH encoded signal having the error when the identifying of the bit locations is ceased.

Abstract: Efficient address generation for interleaver and de-interleaver. The present invention performs interleaving and de-interleaving, at opposite ends of a communication channel, by employing an efficient address generation scheme that is adaptable across a wide variety of applications and platforms. The present invention is particularly applicable to communication channels that exhibit a degree of bursty type noise. By employing interleaving and de-interleaving at the opposite ends of the communication channel, the present invention is able to offer a degree of protection against data corruption that may be caused within the communication channel. The present invention allows convolutional interleaving and de-interleaving operation on a code word by code word basis. The present invention provides for very efficient address generation for RAM based convolutional interleaving and de-interleaving.

Abstract: A differential GPS or GLONASS system (collectively referred to herein as a ‘GPS system’) is implemented for use by a base station of a wireless telephone system (e.g., by a cellular telephone base station). Using the differential GPS system, a differential location ‘correction’ factor is determined based on a difference between a received GPS location signal and a known fixed location of a GPS system receiver for the base station. A differential GPS correction signal containing the correction factor is transmitted to any or all cellular telephone users of that base station to allow the cellular telephones to improve the accuracy of location information independently measured by GPS receivers located in each of the cellular telephones.

Abstract: The present invention provides a hardware accelerator of a DSP with a parameter RAM memory for storing the parameters required for the various operating conditions of the accelerator. The hardware accelerator can easily and without modification accommodate design changes such as the need to support additional ADSL lines.

Abstract: A method or apparatus for decoding of a BCH encoded signal begins by determining whether the received BCH encoded signal includes error. The decoding process continues when the received BCH encoded signal includes error by determining whether the error is correctable. This may be done by determining a number of errors of the received BCH encoded signal, identifying bit locations of the received BCH encoded signal having the error; counting the number of bit locations of the received BCH encoded signal having the error, comparing the number of errors to the number of bit locations of the received BCH encoded signal having the error, when the number of bit locations of the received BCH encoded signal having the error equals the number of errors, ceasing the identifying of the bit locations of the received BCH encoded signal having the error, and correcting information contained in the bit locations of the received BCH encoded signal having the error when the identifying of the bit locations is ceased.

Abstract: A method or apparatus for error identification of a BCH encoded signal includes processing that begins by receiving a BCH encoded signal in a binary polynomial format to produce a received polynomial. The processing then continues by converting the received polynomial into a plurality of error identifying polynomials. The processing then continues by recursively processing the plurality of binary error identifying polynomials to produce a plurality of error identifying values. The processing then continues by processing the plurality of error identifying values to produce an error locator polynomial that represents error in the received polynomial. The processing then continues by evaluating the error locator polynomial to identify the bit location of the error in the BCH encoded signal. The processing then continues by correcting the BCH encoded signal based on the bit location of the error.

Abstract: A programmable state machine of an application specific integrated circuit (ASIC) is programmed by enabling the scan mode of the integrated circuit. The process of programming the state machine continues by loading, through at least one scan chain to which the state machine is coupled, at least one timing sequence instruction into scan capable registers of the state machine. Once the at least one timing sequence instruction has been loaded into the scan capable registers, the scan mode is disabled and normal mode of the integrated circuit is resumed.