Abstract: An apparatus to facilitate real-time playback of point cloud sequence data is disclosed. The apparatus comprises one or more processors to receive point cloud data of a captured scene, decompose the point cloud data into a plurality of point cloud patches, wherein each point cloud patch is associated with an object in the scene and includes contextual information regarding the point cloud patch, encode each of the point cloud patches via a deep-learning based algorithm to generate encoded point cloud patches, receive a viewpoint selection from a client, assign a priority to data chunks within each encoded point cloud patch based on the viewpoint selection and the contextual information and transmit the data chunks to the client based on the assigned priority.

Abstract: The On-demand Virtualized Data Recovery Apparatuses, Methods and Systems (“OVDR”) transforms data recovery request, mailbox backup data selection response inputs via OVDR components into mailbox backup data selection request, data recovery response outputs. A mailbox data recovery request datastructure associated with a user is obtained. Available mailbox backup data accessible to the user is determined. A selection of a subset of the available mailbox backup data to recover is obtained. A temporary mailbox environment associated with the mailbox data recovery request datastructure is spawned. A mailbox, corresponding to a mailbox account included in the selected subset of the available mailbox backup data, is created on the temporary mailbox environment. Mailbox data items, corresponding to mailbox data items associated with the mailbox account that are included in the selected subset of data, are restored to the created mailbox.

Abstract: The On-demand Virtualized Data Recovery Apparatuses, Methods and Systems (“OVDR”) transforms data recovery request, mailbox backup data selection response inputs via OVDR components into mailbox backup data selection request, data recovery response outputs. A mailbox data recovery request datastructure associated with a user is obtained. Available mailbox backup data accessible to the user is determined. A selection of a subset of the available mailbox backup data to recover is obtained. A temporary mailbox environment associated with the mailbox data recovery request datastructure is spawned. A mailbox, corresponding to a mailbox account included in the selected subset of the available mailbox backup data, is created on the temporary mailbox environment. Mailbox data items, corresponding to mailbox data items associated with the mailbox account that are included in the selected subset of data, are restored to the created mailbox.

Abstract: The Multiclient Backup Replication Apparatuses, Methods and Systems (“MBR”) transforms pairing request, replication data stream inputs via MBR components into pairing response, replication confirmation outputs. A replication notification for a snapshot of a backup volume at a source node is obtained. A source node named pipe for the snapshot is created. A priority for the snapshot is determined. When appropriate to send the snapshot to a replication target node, snapshot data is read from the source node named pipe and serialized into chunks Chunks associated with the snapshot and other snapshots are multiplexed into a replication data stream and sent to the replication target node via a persistent network connection. The replication data stream is received by the replication target node and chunks associated with the snapshot are deserialized. A replication target node named pipe for the snapshot is created and used to write snapshot data to a replication volume.

Abstract: The Multiclient Backup Replication Apparatuses, Methods and Systems (“MBR”) transforms pairing request, replication data stream inputs via MBR components into pairing response, replication confirmation outputs. A replication notification for a snapshot of a backup volume at a source node is obtained. A source node named pipe for the snapshot is created. A priority for the snapshot is determined. When appropriate to send the snapshot to a replication target node, snapshot data is read from the source node named pipe and serialized into chunks Chunks associated with the snapshot and other snapshots are multiplexed into a replication data stream and sent to the replication target node via a persistent network connection. The replication data stream is received by the replication target node and chunks associated with the snapshot are deserialized. A replication target node named pipe for the snapshot is created and used to write snapshot data to a replication volume.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

Abstract: A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

Abstract: A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

Abstract: Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.

Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

Abstract: A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.