Abstract: A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.

Abstract: Programmable logic devices (PLDs) including self-repairing RAM circuits, and methods of automatically replacing defective columns in RAM arrays. A RAM circuit including redundant columns is tested during the PLD configuration sequence using a built in self test (BIST) procedure. If a defective column is detected, an error flag is stored in an associated volatile memory circuit. After the BIST procedure is complete, the PLD configuration process continues. The presence of the error flag causes the configuration data to bypass the defective column and to be passed directly into a replacement column. The configuration process continues until the remainder of the circuit is configured, including the redundant column. In other embodiments, the BIST procedure is initiated independently from the PLD configuration process. When a defective column is detected, user operation resumes with data being shunted from the defective column to a redundant column in a fashion transparent to the user.

Abstract: An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.

Abstract: A buffer memory status detection circuit has a binary logic gate (e.g. an OR gate) coupled to a comparator output signal that is asserted when a sum of a first address pointer of a FIFO memory array plus a first offset equals a second address pointer, and to a reset signal. Binary logic provides a binary output (i.e. “0” or “1”) in a first clock domain to two synchronization registers in series that convert the output to a second clock domain. An optional pipeline register improves timing of the output in the second clock domain, and is particularly desirable for use with high-speed clocks.

Abstract: A system for gray-code counting in an integrated circuit such as a programmable logic device uses a binary adder coupled to a binary counter output and to a selected binary offset value. The binary adder provides a binary sum that is converted to a gray code value by a binary-to-gray converter. The gray code value represents the binary sum output.

Abstract: An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.