Patents by Inventor Weddie Pacio Aquien

Weddie Pacio Aquien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6750534
    Abstract: A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: June 15, 2004
    Assignee: ST Assembly Test Services Ltd
    Inventors: Weddie Pacio Aquien, Loreto Y. Cantillep, Setho Sing Fee
  • Patent number: 6543127
    Abstract: In accordance with the objectives of the invention a new method and apparatus is provide for assuring contact balls coplanarity. The process and apparatus for coplanarity inspection is integrated with the current processing step of BGA device singulation and pick-and-place, thereby eliminating the need for a separate processing step that is typically required for the coplanarity inspection.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: April 8, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Antonio B. Dimaano, Jr., Weddie Pacio Aquien, John Briar
  • Publication number: 20020093095
    Abstract: A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.
    Type: Application
    Filed: March 15, 2002
    Publication date: July 18, 2002
    Applicant: ST ASSEMBLY TEST SERVICES PTE LTD
    Inventors: Weddie Pacio Aquien, Loreto Y. Cantillep, Setho Sing Fee
  • Patent number: 6403401
    Abstract: A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: June 11, 2002
    Assignee: St Assembly Test Services Pte Ltd
    Inventors: Weddie Pacio Aquien, Loreto Y. Cantillep, Setho Sing Fee