Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Abstract: A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.

Abstract: A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Abstract: Techniques for serial interface charging are described. An apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger control circuit coupled to the serial interface, the charger control circuit arranged to operate in a charging mode or an on-the-go (OTG) mode based on information received from the serial interface. Another apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger circuit coupled to the serial interface, the charger circuit arranged to operate in a first charging mode or a second charging mode based on information received from the serial interface, the information comprising characteristics of a device coupled to the serial interface. Other embodiments are described and claimed.

Abstract: Techniques for serial interface charging are described. An apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger control circuit coupled to the serial interface, the charger control circuit arranged to operate in a charging mode or an on-the-go (OTG) mode based on information received from the serial interface. Another apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger circuit coupled to the serial interface, the charger circuit arranged to operate in a first charging mode or a second charging mode based on information received from the serial interface, the information comprising characteristics of a device coupled to the serial interface. Other embodiments are described and claimed.

Abstract: Techniques for serial interface charging are described. An apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger control circuit coupled to the serial interface, the charger control circuit arranged to operate in a charging mode or an on-the-go (OTG) mode based on information received from the serial interface. Another apparatus may comprise, for example, a serial interface such as a thunderbolt interface and a charger circuit coupled to the serial interface, the charger circuit arranged to operate in a first charging mode or a second charging mode based on information received from the serial interface, the information comprising characteristics of a device coupled to the serial interface. Other embodiments are described and claimed.