Patents by Inventor Wee Hoo Cheah
Wee Hoo Cheah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190139422Abstract: A drone positioning system includes a processor subsystem and memory comprising instructions, which when executed by the processor subsystem, cause the processor subsystem to perform the operations comprising: transmitting, from an operation drone, a request message to a plurality of companion drones; receiving a response message from each of the plurality of companion drones, each response message including: a first timestamp indicating when the response message was sent from the corresponding companion drone and a first geoposition of the corresponding companion drone; calculating a first distance to each of the plurality of companion drones using the first timestamps of respective response messages from each of the plurality of companion drones; calculating an estimated geoposition of the operation drone from the respective first distances and the respective first geopositions of the companion drones; and assisting navigation of the operation drone using the estimated geoposition.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Wee Hoo Cheah, David W. Browning
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Patent number: 10198333Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.Type: GrantFiled: December 23, 2010Date of Patent: February 5, 2019Assignee: INTEL CORPORATIONInventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Brian Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
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Patent number: 9098643Abstract: In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.Type: GrantFiled: December 19, 2013Date of Patent: August 4, 2015Assignee: Intel CorporationInventors: Wee Hoo Cheah, Chun Hung Pang, Kuan Loon Tan
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Publication number: 20150127983Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.Type: ApplicationFiled: December 23, 2010Publication date: May 7, 2015Applicant: INTEL CORPORATIONInventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Briar Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
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Publication number: 20140108845Abstract: In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 19, 2013Publication date: April 17, 2014Inventors: Wee Hoo Cheah, Chun Hung Pang, Kuan Loon Tan
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Patent number: 8621129Abstract: In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.Type: GrantFiled: December 9, 2010Date of Patent: December 31, 2013Assignee: Intel CorporationInventors: Wee Hoo Cheah, Chun Hung Pang, Kuan Loon Tan
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Publication number: 20120151109Abstract: In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 9, 2010Publication date: June 14, 2012Inventors: Wee Hoo Cheah, Chun Hung Pang, Kuan Loon Tan
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Publication number: 20110102442Abstract: Screen recording may be implemented with better security, performance, power savings and cost without the need of additional software to support the screen recording feature, in some embodiments, by using a keyboard, video, mouse functionality already provided in a computer system chipset on a motherboard. Frames of video may be stored on that system or, in some cases, may be selectively provided to a local area network.Type: ApplicationFiled: November 4, 2009Publication date: May 5, 2011Inventors: Ahmed Rafeek Bin Ahmad Ibrahim, Wee Hoo Cheah