Abstract: A Li-ion thin film microbattery, a microbattery array, a method of fabricating a Li-ion thin film microbattery and a method of fabricating a microbattery array. The Li-ion thin film microbattery comprises a Li-free cathode comprising a transition metal oxide thin film; an anode comprising a lithiated Ge or Si thin film; and an electrolyte film disposed between the cathode and the anode; wherein a Li-source of the Li-ion thin film microbattery is provided by means of the lithiated Ge or Si thin film.

Abstract: A Li-ion thin film microbattery, a microbattery array, a method of fabricating a Li-ion thin film microbattery and a method of fabricating a microbattery array. The Li-ion thin film microbattery comprises a Li-free cathode comprising a transition metal oxide thin film; an anode comprising a lithiated Ge or Si thin film; and an electrolyte film disposed between the cathode and the anode; wherein a Li-source of the Li-ion thin film microbattery is provided by means of the lithiated Ge or Si thin film.

Abstract: There is provided a microarray comprising a plurality of active agents immobilized onto an array of porous nanostructures, wherein each nanostructure has a network of pores that extends throughout the thickness of said nano structure.

Abstract: A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm.

Abstract: Methods for altering the wetting property of the surface of a substrate are disclosed. The methods can include the step of providing an array of nanostructures on the substrate, each nanostructure having a proximal end adjacent to the substrate and a distal end opposite to the proximal end. The methods can also include the step of moving the distal ends of at least one subset of the array of nanostructures towards each other to form at least one nanostructure cluster. The nanostructures of each cluster have distal ends that are spaced closer to each other relative to the respective proximal ends of the adjacent nanostructures, the nanostructure cluster altering the wetting property of the substrate.

Abstract: A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm.

Abstract: A memory gate stack structure (100) comprising a substrate layer (102) comprising a silicon-based material, a tunnel layer (104) formed on the substrate layer, a charge storage layer (106) formed on the tunnel layer and comprising a hafnium-aluminium-oxide-based material, a blocking layer (108) formed on the charge storage layer, and a gate layer (110) formed on the blocking layer.

Abstract: Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.

Abstract: A Flash memory is provided having a trilayer structure of rapid thermal oxide/germanium (Ge) nanocrystals in silicon dioxide (SiO2)/sputtered SiO2 cap with demonstrated via capacitance versus voltage (C-V) measurements having memory hysteresis due to Ge nanocrystals in the middle layer of the trilayer structure. The Ge nanocrystals are synthesized by rapid thermal annealing of a co-sputtered Ge+SiO2 layer.

Abstract: A Flash memory is provided having a trilayer structure of rapid thermal oxide/germanium (Ge) nanocrystals in silicon dioxide (SiO2)/sputtered SiO2 cap with demonstrated via capacitance versus voltage (C-V) measurements having memory hysteresis due to Ge nanocrystals in the middle layer of the trilayer structure. The Ge nanocrystals are synthesized by rapid thermal annealing of a co-sputtered Ge+SiO2 layer.