Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

Abstract: A package for reducing signal cross talk between wire bonds of semiconductor packages. The package includes a semiconductor die having a plurality of bond pads formed thereon. The bond pads arranged in a first subset of bond pads and a second subset of bond pads. The package also includes a substrate having a plurality of contact points, the plurality of contact points are arranged in a first subset of contact points and a second subset of contact points. To reduce signal cross talk, the wire bonds are arranged such that a first subset of wire bonds are electrically coupled between the first subset of bond pads and the first subset of the contact points. The first subset of wire bonds have ball bonds formed on the first subset of bond pads and stitch bonds formed on the first subset of contact points respectively. A second subset of wire bonds are electrically coupled between the second subset of bond pads and the second subset of the contact points.

Abstract: A semiconductor package for reducing signal cross talk between wire bonds of semiconductor packages by using a tier of input-output power bond pads between two tiers of signal bond pads. The package includes a substrate having a first surface and a second surface and a die attach area on the first surface of the substrate. A first tier of signal contacts is arranged around the periphery of the die attach on the first surface of the substrate. A second tier of signal contacts is arranged around the periphery of the die attach area on the first surface of the substrate. A power contact tier is also arranged around the periphery of the die attach area on the first surface of the substrate. The power contact tier is arranged between the first tier of signal contacts and the second tier of signal contacts to reduce signal noise and cross talk between the signal bond wires of the first tier and the second tier.

Abstract: A method wherein a substrate with plating tails is formed or otherwise provided, such as by performing a conventional electroplating process. Subsequently, a laser is used to remove some or all of the plating tails or a portion of some or all of the plating tails. If portions or remnants of the plating tails are to remain, the plating tails can be connected to ground. By connecting the remnants of the plating tails to ground, an electrical performance enhancement can be realized. Specifically, additional shielding in the package can be provided. Furthermore, the plating tails can be specifically designed to enhance the amount of shielding they provide.