Abstract: A plurality of groups of first flip-flops (group 40 of flip-flops A1–An?1 for each of channels CIA–CIC) store input data clocked in response to first clock signals (A–C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group 60 of flip-flops B1–Bn for each of channels CIA–CIC) store the input data from the first flip-flops in response to the first enable signals and first clock signals. A second enable signal (Slide_en) is generated in response to a second clock signal (D) and the first enable signal. A plurality of groups of third flip-flops (group 80 for each of channels CIA–CIC) store the data in response to the second enable signal and second clock signal. The data is transmitted in serial form at the rate of the second clock signal.

Abstract: A method and system for identifying a bit pattern in a data stream including a plurality of bits each having a first or second state, the method includes identifying a number of mismatching bits, within a subset of the plurality of bits, having the first state and corresponding to a bit having the second state within the pattern; identifying a number of bits in the subset having the first state; and, identifying a number of bits in the pattern having the second state. A number of matches of between the subset and the pattern is dependent on the identified number of mismatching bits, the identified number of bits in the subset having the first state and the identified number of bits in the pattern having the second state.

Abstract: A plurality of groups of first flip-flops (group 40 of flip-flops A1-An?1 for each of channels CIA-CIC) store input data clocked in response to first clock signals (A-C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group 60 of flip-flops B1-Bn for each of channels CIA-CIC) store the input data from the first flip-flops in response to the first enable signals and first clock signals. A second enable signal (Slide_en) is generated in response to a second clock signal (D) and the first enable signal. A plurality of groups of third flip-flops (group 80 for each of channels CIA-CIC) store the data in response to the second enable signal and second clock signal. The data is transmitted in serial form at the rate of the second clock signal.

Abstract: A plurality of groups of first flip-flops (group 40 of flip-flops A1-An−1 for each of channels CIA-CIC) store input data clocked in response to first clock signals (A-C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group 60 of flip-flops B1-Bn for each of channels CIA-CIC) store the input data from the first flip-flops in response to the first enable signals and first clock signals. A second enable signal (Slide_en) is generated in response to a second clock signal (D) and the first enable signal. A plurality of groups of third flip-flops (group 80 for each of channels CIA-CIC) store the data in response to the second enable signal and second clock signal. The data is transmitted in serial form at the rate of the second clock signal.

Abstract: A method and system for identifying a bit pattern in a data stream including a plurality of bits each having a first or second state, the method includes identifying a number of mismatching bits, within a subset of the plurality of bits, having the first state and corresponding to a bit having the second state within the pattern; identifying a number of bits in the subset having the first state; and, identifying a number of bits in the pattern having the second state. A number of matches of between the subset and the pattern is dependent on the identified number of mismatching bits, the identified number of bits in the subset having the first state and the identified number of bits in the pattern having the second state.