Abstract: A protection circuit for protecting DCDC converter with a power MOS transistor from start-up in-rush current includes a coupling capacitor and a voltage clamping circuit. By using the coupling capacitor to turn-off the power MOS transistor, there is no current consumed during the normal operation of the circuit. Enable signal or leakage current circuit is used to discharge the capacitor so that the circuitry can work in another turning-on of power supply.

Abstract: An output short to ground protection circuit protects an electronic device when it is short circuited to ground. The protection circuit has an NMOS transistor coupled to the output power transistor. A fixed voltage generator is connected to a gate terminal of the NMOS transistor. A first voltage clamping circuit and a second voltage clamping circuit are provided. The voltage clamping circuits are utilized so as to limit the current outputted by the output power transistor when the short circuit occurs.

Abstract: A protection circuit for protecting DCDC converter with a power MOS transistor from start-up in-rush current includes a coupling capacitor and a voltage clamping circuit. By using the coupling capacitor to turn-off the power MOS transistor, there is no current consumed during the normal operation of the circuit. Enable signal or leakage current circuit is used to discharge the capacitor so that the circuitry can work in another turning-on of power supply.

Abstract: A slew rate control circuit in output driver of switching circuit to prevent power ground undershoot is introduced. The gate capacitance of lower power transistor is first fast discharged to ensure the operation of the output signal. The gate capacitance of lower power transistor is then slowly discharged to limit OUT SLEW RATE. The gate capacitance of lower power transistor is further slowly discharged when the power ground level is below common ground. With above controlling, the gate voltage slew rate of lower power transistor is reduced when the lower power transistor is almost fully turned OFF. Therefore, undershoot at the power ground is avoided. Similar slew rate control circuit can also be derived in output driver of switching circuit to prevent PVCC overshoot.

Abstract: A class D amplifier with output DC offset protection is disclosed. The DC offset protection receives a PWM input signals from the outputs and investigates the PWM output signals whether there is a large DC voltage difference is being reflected on the speaker load. If so, shutdown signal SD will be sent by the DC offset protection to the PWM control logic and gate driver, thus, shutting down the output of the class D system and preventing disastrous condition from being develop across the speaker.

Abstract: A class D amplifier with output DC offset protection is disclosed. The DC offset protection receives a PWM input signals from the outputs and investigates the PWM output signals whether there is a large DC voltage difference is being reflected on the speaker load. If so, shutdown signal SD will be sent by the DC offset protection to the PWM control logic and gate driver, thus, shutting down the output of the class D system and preventing disastrous condition from being develop across the speaker.

Abstract: A slew rate control circuit in output driver of switching circuit to prevent power ground undershoot is introduced. The gate capacitance of lower power transistor is first fast discharged to ensure the operation of the output signal. The gate capacitance of lower power transistor is then slowly discharged to limit OUT SLEW RATE. The gate capacitance of lower power transistor is further slowly discharged when the power ground level is below common ground. With above controlling, the gate voltage slew rate of lower power transistor is reduced when the lower power transistor is almost fully turned OFF. Therefore, undershoot at the power ground is avoided. Similar slew rate control circuit can also be derived in output driver of switching circuit to prevent PVCC overshoot.

Abstract: A differential input Class D audio power amplifier incorporating a differential error amplifier is introduced. In response of differential input signal, this differential error amplifier generates two error signals, which subsequently generates final output signal. This architecture makes it the effect of feedback signal error correction doubled, which helps in achieving good THD. In addition, input port of this architecture is also compatible with single-ended signal. A pop noise suppression technique for this differential input Class D audio power amplifier is also introduced.

Abstract: A differential input Class D audio power amplifier incorporating a differential error amplifier is introduced. In response of differential input signal, this differential error amplifier generates two error signals, which subsequently generates final output signal. This architecture makes it the effect of feedback signal error correction doubled, which helps in achieving good THD. In addition, input port of this architecture is also compatible with single-ended signal. A pop noise suppression technique for this differential input Class D audio power amplifier is also introduced.