Patents by Inventor Wee Sien Hong
Wee Sien Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8264807Abstract: A protection circuit for protecting DCDC converter with a power MOS transistor from start-up in-rush current includes a coupling capacitor and a voltage clamping circuit. By using the coupling capacitor to turn-off the power MOS transistor, there is no current consumed during the normal operation of the circuit. Enable signal or leakage current circuit is used to discharge the capacitor so that the circuitry can work in another turning-on of power supply.Type: GrantFiled: March 26, 2010Date of Patent: September 11, 2012Assignees: Panasonic Corporation, Panasonic Semiconductor Asia Pte. Ltd.Inventors: Wee Sien Hong, Jiong Fu, Andi Soemarli Rasak Lie
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Publication number: 20110234184Abstract: A protection circuit for protecting DCDC converter with a power MOS transistor from start-up in-rush current includes a coupling capacitor and a voltage clamping circuit. By using the coupling capacitor to turn-off the power MOS transistor, there is no current consumed during the normal operation of the circuit. Enable signal or leakage current circuit is used to discharge the capacitor so that the circuitry can work in another turning-on of power supply.Type: ApplicationFiled: March 26, 2010Publication date: September 29, 2011Applicants: PANASONIC CORPORATION, PANASONIC SEMICONDUCTOR ASIA PTE. LTD.Inventors: Wee Sien HONG, Jiong FU, Andi Soemarli Rasak LIE
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Publication number: 20110235222Abstract: An output short to ground protection circuit protects an electronic device when it is short circuited to ground. The protection circuit has an NMOS transistor coupled to the output power transistor. A fixed voltage generator is connected to a gate terminal of the NMOS transistor. A first voltage clamping circuit and a second voltage clamping circuit are provided. The voltage clamping circuits are utilized so as to limit the current outputted by the output power transistor when the short circuit occurs.Type: ApplicationFiled: March 26, 2010Publication date: September 29, 2011Applicants: PANASONIC CORPORATION, PANASONIC SEMICONDUCTOR ASIA PTE. LTD.Inventors: Wee Sien HONG, Weijie LI, Guo Lei YU
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Patent number: 7696808Abstract: A slew rate control circuit in output driver of switching circuit to prevent power ground undershoot is introduced. The gate capacitance of lower power transistor is first fast discharged to ensure the operation of the output signal. The gate capacitance of lower power transistor is then slowly discharged to limit OUT SLEW RATE. The gate capacitance of lower power transistor is further slowly discharged when the power ground level is below common ground. With above controlling, the gate voltage slew rate of lower power transistor is reduced when the lower power transistor is almost fully turned OFF. Therefore, undershoot at the power ground is avoided. Similar slew rate control circuit can also be derived in output driver of switching circuit to prevent PVCC overshoot.Type: GrantFiled: December 4, 2007Date of Patent: April 13, 2010Assignees: Panasonic Corporation, Panasonic Semiconductor Asia Pte. Ltd.Inventors: Shiah Siew Wong, Wee Sien Hong, Tien Yew Kang, Jing Sun
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Patent number: 7692488Abstract: A class D amplifier with output DC offset protection is disclosed. The DC offset protection receives a PWM input signals from the outputs and investigates the PWM output signals whether there is a large DC voltage difference is being reflected on the speaker load. If so, shutdown signal SD will be sent by the DC offset protection to the PWM control logic and gate driver, thus, shutting down the output of the class D system and preventing disastrous condition from being develop across the speaker.Type: GrantFiled: February 28, 2008Date of Patent: April 6, 2010Assignees: Panasonic Corporation, Panasonic Semiconductor Asia Pte. Ltd.Inventors: Shiah Siew Wong, Wee Sien Hong, Chee Kuan Leong, Narciso Repollo Semira
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Publication number: 20090219090Abstract: A class D amplifier with output DC offset protection is disclosed. The DC offset protection receives a PWM input signals from the outputs and investigates the PWM output signals whether there is a large DC voltage difference is being reflected on the speaker load. If so, shutdown signal SD will be sent by the DC offset protection to the PWM control logic and gate driver, thus, shutting down the output of the class D system and preventing disastrous condition from being develop across the speaker.Type: ApplicationFiled: February 28, 2008Publication date: September 3, 2009Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., PANASONIC SEMICONDUCTOR ASIA PTE. LTD.Inventors: Shiah Siew WONG, Wee Sien HONG, Chee Kuan LEONG, Narciso Repollo SEMIRA
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Publication number: 20090140796Abstract: A slew rate control circuit in output driver of switching circuit to prevent power ground undershoot is introduced. The gate capacitance of lower power transistor is first fast discharged to ensure the operation of the output signal. The gate capacitance of lower power transistor is then slowly discharged to limit OUT SLEW RATE. The gate capacitance of lower power transistor is further slowly discharged when the power ground level is below common ground. With above controlling, the gate voltage slew rate of lower power transistor is reduced when the lower power transistor is almost fully turned OFF. Therefore, undershoot at the power ground is avoided. Similar slew rate control circuit can also be derived in output driver of switching circuit to prevent PVCC overshoot.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., PANASONIC SEMICONDUCTOR ASIA PTE., LTD.Inventors: Shiah Siew WONG, Wee Sien HONG, Tien Yew KANG, Jing SUN
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Patent number: 7446603Abstract: A differential input Class D audio power amplifier incorporating a differential error amplifier is introduced. In response of differential input signal, this differential error amplifier generates two error signals, which subsequently generates final output signal. This architecture makes it the effect of feedback signal error correction doubled, which helps in achieving good THD. In addition, input port of this architecture is also compatible with single-ended signal. A pop noise suppression technique for this differential input Class D audio power amplifier is also introduced.Type: GrantFiled: August 17, 2006Date of Patent: November 4, 2008Assignees: Matsushita Electric Industrial Co., Ltd., Panasonic Semiconductor Asia Pte. Ltd.Inventors: Shiah Siew Wong, Wee Sien Hong, Tien Yew Kang, Chew Yuan Woong
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Publication number: 20080042743Abstract: A differential input Class D audio power amplifier incorporating a differential error amplifier is introduced. In response of differential input signal, this differential error amplifier generates two error signals, which subsequently generates final output signal. This architecture makes it the effect of feedback signal error correction doubled, which helps in achieving good THD. In addition, input port of this architecture is also compatible with single-ended signal. A pop noise suppression technique for this differential input Class D audio power amplifier is also introduced.Type: ApplicationFiled: August 17, 2006Publication date: February 21, 2008Applicants: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., Panasonic Semiconductor Asia Pte. Ltd.Inventors: Shiah Siew WONG, Wee Sien HONG, Tien Yew KANG, Chew Yuan WOONG