Abstract: Integrated circuit devices, methods, and circuitry for configuring input/output (IO) circuitry for boundary scan chain testing is provided. An integrated circuit device may include a configuration register and IO configuration selector circuitry. The configuration register may define a voltage level of the IO circuitry based on a code stored in the configuration register. The IO configuration selector circuitry may determine the code based on a power-on-reset (POR) instruction.

Abstract: Integrated circuit devices, methods, and circuitry for performing boundary scan chain testing is provided. Such an integrated circuit device may include a Joint Test Action Group (JTAG) network, a first input/output (IO) subsystem, and a second IO subsystem. The first IO subsystem includes first segmented boundary scan chain circuitry that can receive JTAG Test Data In (TDI) signals from a main JTAG test access port (TAP) of the JTAG network and use the JTAG TDI signals to perform a first boundary scan chain test. The second IO subsystem includes second segmented boundary scan chain circuitry that can receive the JTAG TDI signals from the main JTAG TAP of the JTAG network and use the JTAG TDI signals to perform a second boundary scan chain test in parallel with the first boundary scan chain test.

Abstract: An integrated circuit includes first and second pads, a buffer circuit coupled to the first pad, a first pass gate circuit coupled to the first pad and to the buffer circuit, a second pass gate circuit coupled to the second pad, and a test bus coupled to the first pass gate circuit and the second pass gate circuit. The first pass gate circuit and the second pass gate circuit are configurable to couple the second pad to the buffer circuit through the test bus during a test of the buffer circuit that is performed using the second pad.