Abstract: The technology disclosed herein provides a method for generating an on-cylinder limit (OCLIM), the method including performing servo certification of a plurality of drives in a storage device to generate servo adaptive parameters (SAPs) by heads, generating a plurality of read adjust parameters (RAPs) by heads for the plurality of drives, generating an interim OCLIM value based on the SAPs by heads and RAPs by zones, and operating a disc drive write element using the interim OCLIM value.

Abstract: The technology disclosed herein provides a method for generating an on-cylinder limit (OCLIM), the method including performing servo certification of a plurality of drives in a storage device to generate servo adaptive parameters (SAPs) by heads, generating a plurality of read adjust parameters (RAPs) by heads for the plurality of drives, generating an interim OCLIM value based on the SAPs by heads and RAPs by zones, and operating a disc drive write element using the interim OCLIM value.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The technology disclosed herein provides a method for generating an on-cylinder limit (OCLIM), the method including performing servo certification of a plurality of drives in a storage device to generate servo adaptive parameters (SAPs) by heads, generating a plurality of read adjust parameters (RAPs) by heads for the plurality of drives, generating an interim OCLIM value based on the SAPs by heads and RAPs by zones, and operating a disc drive write element using the interim OCLIM value.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A method for performing a flaw scan test on a hard disk drive is disclosed. The hard disk drive includes a magnetic recording medium and spindle motor associated with a predetermined rated speed. The method includes writing a test pattern to the magnetic recording medium while operating the spindle motor at a speed greater than the predetermined rated speed. The method also includes reading the test pattern at the greater speed and detecting flaws in response to reading the test pattern.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A transistor includes a substrate and a gate over the substrate. The transistor further includes a source and a drain over the substrate on opposite sides of the gate. The transistor further includes a channel region beneath the gate separating the source from the drain, the channel region having a channel width with respect to a surface of the substrate greater than a width of the gate with respect to the surface of the substrate. The transistor further includes a silicide over a first portion of the drain, wherein a second portion of the drain, closer to the gate than the first portion, is an unsilicided region.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A method of preventing contact metal from protruding into neighboring gate devices to affect work functions of the neighboring gate devices is provided includes forming a gate structure. Forming the gate structure includes forming a work function layer, and forming a gate metal layer having a void, wherein the work function layer surrounds the gate metal layer. The method further includes forming a contact plug having a contact metal directly on the gate metal layer of the first gate stack, wherein the contact metal protrudes into the void, and the work function layer prevents the contact metal from protruding into a second gate stack.

Abstract: Method and apparatus for positioning shingled magnetic recording (SMR) tracks on a rotatable data storage medium. In some embodiments, a first band of partially overlapping tracks is written the medium at a first track pitch. An adjacent, second band of partially overlapping tracks is written to the medium at the first track pitch. The second band has a first written track at a second track pitch with respect to a last written track in the first band. The second track pitch is determined in response to an error rate established for a test track using an adjacent track written at the first track pitch.

Abstract: A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width. Each gate electrode of the first set of gate electrodes has a first gate width. The method further includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width. Each gate electrode of the second set of gate electrodes has a second gate width greater than the first gate width.