Abstract: A moisture-absorbing dry electrode and smart clothing. The moisture-absorbing dry electrode includes a substrate and a moisture-absorbing electrode. The substrate has a surface. The moisture-absorbing electrode includes at least one moisture-absorbing conductive film, and the moisture-absorbing conductive film is used to absorb moisture and disposed on the surface of the substrate. The material of the moisture-absorbing conductive film includes a uniform mixture of carbon paste, a moisture-absorbing material and a cross-linking agent, and the moisture-absorbing material includes a nanomaterial or an inorganic adsorbent material, or a combination thereof.

Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.

Abstract: A clamping device includes a positioning shank, a clamping module pivotally connected with the positioning shank, an ultrasonic searcher clamped by the clamping module, a fixture mounted on the positioning shank, a needle holder pivotally connected with the fixture, and a needle hub mounted on the needle holder. The clamping module includes a positioning frame, multiple abutting pieces mounted in the positioning frame, and multiple push knobs rotatably mounted on the positioning frame and pressing the abutting pieces. The abutting pieces are moved to press the ultrasonic searcher. The push knobs are rotated to move the abutting pieces forward and backward. The abutting pieces are pushed inward by the push knobs so that the clamping module is used to mount ultrasonic searchers of different sizes.

Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a first electrically conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a mesa structure disposed in the planar device region and fin-shaped structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate and includes a first portion which is disposed on the planar device region and covers a sidewall of the mesa structure, and the isolation structure further includes a second portion which is disposed on the fin device region and located between the fin-shaped structures. The first electrically conductive structure is disposed on the planar device region. The first electrically conductive structure is partly disposed above the mesa structure in a vertical direction and partly disposed above the first portion of the isolation structure in the vertical direction.

Abstract: Methods, systems, and devices for providing computer implemented services are disclosed. To provide the computer implemented services, an identification of a startup of a data processing system may be made. Based on the identification, a determination may be made regarding whether a device is present in an expansion slot of the data processing system. If the device is present, then another determination may be made regarding whether identification information is able to be obtained from the device. If obtained, the identification information may be interpreted to obtain communication link bifurcation settings for the device. Default communication link training settings may then be updated based on the bifurcation settings to obtain updated training settings. Communication link training may then be initiated for a communication link using the updated training settings.

Abstract: In a method of manufacturing a chip structure, a first carrier is attached on a back surface of a wafer, the wafer is diced into individual dies and there is a groove formed between the adjacent dies, then a second carrier is attached on an active surface of the wafer and the first carrier is removed to expose the groove, a back surface and a lateral surface of each of the dies, a heat dissipation cover is formed on the back surface and the lateral surface of each of the dies to obtain chip structures. The heat dissipation cover is provided to increase heat dissipation efficiency of the dies and prevent formation of metal debris which may contaminate the dies. Furthermore, the heat dissipation cover is prevented from being separated from the die.

Abstract: A composite cathode preparation method is provided. The composite cathode preparation method includes steps of: (a) providing a cathode material, a solid electrolyte, a conductive carbon, and an alcohol solvent, wherein the cathode material includes a plurality of first particles and has a composition of Li[NiaCobMncAld]O2, a+b+c+d=1, 0.8<a?1, 0?b<1, 0?c<1, and 0?d<1, wherein the solid electrolyte has a composition of Li3InClxFy, x+y?6, 0?x?6, and 0?y?3; (b) mixing the cathode material, the solid electrolyte, the conductive carbon, and the alcohol solvent to form a first slurry; (c) mixing the first slurry and a binder to form a second slurry; and (d) subjecting the second slurry to a heat treatment and remove the alcohol solvent to form the composite cathode, wherein the composite cathode includes a plurality of second particles, each of the second particles includes one of the plurality of first particles and the solid electrolyte coated on the first particles.

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

Abstract: A wireless communication device is provided. The wireless communication device includes a circuit board, an antenna module, a housing and a metal pattern unit. The antenna module is coupled to the circuit board, wherein the antenna module transmits a wireless signal, the antenna module defines a first FOV area and a second FOV area, and the first FOV area differs from the second FOV area. The housing covers the antenna module, wherein a lid portion of the housing corresponds to the first FOV area, and the lid portion has a first equivalent dielectric constant. The metal pattern unit corresponds to the second FOV area, the metal pattern unit causes a second equivalent dielectric constant, and the first equivalent dielectric constant differs from the second equivalent dielectric constant.

Abstract: A multifunctional probe includes a hand-held housing, a signal detector and an array probe. The signal detector is flexibly disposed on the hand-held housing or at its first end. The array probe is disposed at one end (e.g., second end) of the hand-held housing and electrically coupled to the signal detector. The first contact time of the signal detector in contact with the living body may at least partially overlap with the second contact time of the array probe in contact with the living body. The signal detector and the array probe generate the first electronic signal. The multifunctional probe includes a flexibly-connected signal detector and an array probe, which can contact and/or detect the living body at the same time. Thus, the detection efficiency and accuracy are effectively increased. A detection method applied to the multifunctional probe is also provided.

Abstract: A composite electrode and a preparation method thereof are disclosed. The composite electrode includes a composite positive electrode material layer coated on a carrying surface of an electrode plate. The composite positive electrode material layer includes plural positive electrode material particles, a first conductive carbon and a Li-Nafion polymer material. The positive electrode material particles are composed of ternary materials. The first conductive carbon is pre-coated on surfaces of the positive electrode material particles by dry mechanical mixing. A weight percent of the first conductive carbon relative to the positive electrode material particles is ranged from 1 wt. % to 5.5 wt. %. The Li-Nafion polymer material covers the surfaces of the positive electrode material particles and is bonded among the surfaces of the positive electrode material particles. A weight percent of the Li-Nafion polymer material relative to the positive electrode material particles is ranged from 10 wt. % to 20 wt. %.

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

Abstract: A cathode material including a plurality of particles. Each of the plurality of particles includes a core layer and a coating layer coated thereon. The core layer includes a lithium metal oxide material having a composition of Li[NiaCobMncAld]O2, wherein a+b+c+d=1, 0<a<1, 0<b<1, 0?c<1, and 0?d<1. The coating layer includes a solid electrolyte formed by a reaction of a first material on the core layer. The solid electrolyte has a composition of Li3InClxFy, wherein x+y=6, 0<x<6, and 0<y<6. The lithium metal oxide material, the first material, and a solvent are mixed to form a precursor, and the precursor is heat-treated to form the cathode material. The first material includes lithium, indium, chlorine, and fluorine. The lithium metal oxide material and the solid electrolyte have a weight ratio ranged from 1:0.3 to 1:0.6.

Abstract: A semiconductor device package includes a first circuit layer, a first emitting device and a second emitting device. The first circuit layer has a first surface and a second surface opposite to the first surface. The first emitting device is disposed on the second surface of the first circuit layer. The first emitting device has a first surface facing the first circuit layer and a second surface opposite to the first surface. The first emitting device has a first conductive pattern disposed on the first surface of the first emitting device. The second emitting device is disposed on the second surface of the first emitting device. The second emitting device has a first surface facing the second surface of the first emitting device and a second surface opposite to the first surface. The second emitting device has a second conductive pattern disposed on the second surface of the emitting device.