Patents by Inventor Wei-An Liang

Wei-An Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11336427
    Abstract: A circuit of communication interface between dies is provided. The circuit includes a first interface of the first die having a serializer to serialize an input data of N bits a serialized data for transmitting out and a second interface of the second die having a de-serializer to receive and deserialize the serialized data into a de-serialized data. In addition, an interconnection structure connected between the first die and the second die to connect the serializer and the de-serializer, wherein the interconnection structure is an interposer or a redistribution layer of a semiconductor structure to form a parallel bus for transmitting the serialized data in one line of the parallel bus between the first die and the second die. A clock generator provides a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the de-serializer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 17, 2022
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Igor Elkanovich, Yen-Chung T. Chen, Chia-Hsiang Chang, Ting-Hsu Chien, Tsai-Ming Yang, Wei-An Liang, Amnon Parnass
  • Publication number: 20070277997
    Abstract: Layout methods for a substrate are disclosed. In one embodiment, the method includes: defining a first plating line on a non-conducting layer coupled to a first pad; and defining a second plating line on the first conducting layer coupled to a second pad. Along a direction away from the first pad and the second pad, a distance between the first plating line and the second plating line becomes longer. In another embodiment, the method includes: defining a plating line on a non-conducting layer, the plating line being coupled to a pad; and replacing a portion of at least a conducting layer with a non-conducting material, wherein the portion is directly under the plating line.
    Type: Application
    Filed: June 1, 2006
    Publication date: December 6, 2007
    Inventors: Wei-An Liang, Chung-Ju Wu, Yin-Chieh Hsueh