Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a first electrically conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a mesa structure disposed in the planar device region and fin-shaped structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate and includes a first portion which is disposed on the planar device region and covers a sidewall of the mesa structure, and the isolation structure further includes a second portion which is disposed on the fin device region and located between the fin-shaped structures. The first electrically conductive structure is disposed on the planar device region. The first electrically conductive structure is partly disposed above the mesa structure in a vertical direction and partly disposed above the first portion of the isolation structure in the vertical direction.

Abstract: A semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, a first organic layer, a first inorganic layer and a first silicon-containing layer. The third conductive layer is disposed between and electrically isolated from the first conductive layer and the second conductive layer. The first organic layer continuously covers the first conductive layer and the third conductive layer. The first inorganic layer is disposed over the first organic layer. The first silicon-containing layer is inserted between the first organic layer and the first inorganic layer, wherein the second conductive layer is disposed on and disposed in the first organic layer, the first silicon-containing layer and the first inorganic layer, to electrically connect to the first conductive layer.

Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

Abstract: A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi2, a second silicide region on the first silicide region, the second silicide region including TiSix, and a conductive material on the second silicide region.

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

Abstract: A semiconductor structure includes a circuit substrate, at least one semiconductor package, at least one semiconductor device, and a ring structure. The at least one semiconductor package is disposed on the circuit substrate, and the semiconductor package includes a plurality of integrated circuit structures. The at least one semiconductor device, disposed on the circuit substrate and aside the semiconductor package. The ring structure is disposed on the circuit board. The ring structure includes at least one opening pattern corresponding to the semiconductor device.

Abstract: A semiconductor die and methods of forming the same and a package structure are provided. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads over the semiconductor substrate, a passivation layer over the semiconductor substrate and partially covering the plurality of conductive pads, an interconnecting line disposed on the passivation layer, and a plurality of connectors disposed on and electrically connected to the plurality of conductive pads. Each of the plurality of connectors includes a stacked structure of a first conductive pillar and a second conductive pillar disposed directly on the first conductive pillar, wherein a span of the second conductive pillar is smaller than a span of the first conductive pillar, and an orthogonal projection of the second conductive pillar falls within an orthogonal projection of the first conductive pillar, and the interconnecting line is located beside and spaced apart from the plurality of connectors.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: The present disclosure relates to a method for producing a component, preferably for a sporting good, comprising the following steps: providing a polymer; providing a solvent; mixing the polymer with the solvent, thereby producing a liquefied polymer; and curing the liquefied polymer, thereby producing the component. Other embodiments of the disclosure relate to an outsole and a sports shoe obtained by the method according to the disclosure.

Abstract: Disclosed herein is a method for treating and/or preventing a lymphangiogenesis-associated disease in a subject, including administering to the subject a therapeutically effective amount of a dihydrolipoic acid (DHLA)-coated gold nanocluster about 0.1 to 10 nm in diameter. Also disclosed is a method for promoting lymphangiogenesis in a subject, including administering to the subject an effective amount of said DHLA-coated gold nanocluster.

Abstract: A method includes: generating a designed mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming the actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask metrology apparatus including a light source having a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern while the mask is under the alignment.

Abstract: A system for purifying helium gas, a method, and an application. The system includes a first gas-liquid separation device, a primary helium extraction tower, a second gas-liquid separation device, a secondary helium extraction tower, and a nitrogen removal tower, which are in sequential communication. The first gas-liquid separation device performs first treatment to convert helium-containing natural gas into a first gas and first liquid phases; the primary helium extraction tower performs first distillation on the first gas and first liquid phases to obtain a second gas and second liquid phases; the second gas-liquid separation device performs second treatment to convert the second gas phase to a third gas and third liquid phase; the secondary helium extraction tower performs second distillation on the third gas and third liquid phases to obtain crude helium and a fourth liquid phase form which nitrogen is removed by the nitrogen removal tower.

Abstract: A method includes depositing a first metal layer on a package component, wherein the package component comprises a first device die, forming a dielectric layer on the package component, and plating a metal thermal interface material on the first metal layer. The dielectric layer includes portions on opposing sides of the metal thermal interface material. A heat sink is bonded on the metal thermal interface material. The heat sink includes a second metal layer physically joined to the metal thermal interface material.

Abstract: A data storage method, a host system, and a data storage system are disclosed. The method includes the following. An artificial intelligence (AI) model is executed. First data to be stored to a memory storage device is obtained. In response to the first data being generated by the AI model, second data is generated according to the first data, in which the second data includes the first data, and a data amount of the second data is greater than a data amount of the first data. A first write command is sent to the memory storage device according to the second data, so as to instruct the memory storage device to store the second data.

Abstract: A secondary-side controller applied to a flyback power converter prevents a secondary side of the flyback power converter from conducting incorrectly. The secondary-side controller includes a first comparison circuit, a second comparison circuit, and a gate control signal generation circuit. The first comparison circuit generates a first comparison signal according to a drain voltage of a synchronous switch of the secondary side of the flyback power converter and a first parameter. The second comparison circuit generates a ready signal according to the first comparison signal and a resistance of an external resistor. The gate control signal generation circuit generates a gate control signal to the synchronous switch according the ready signal and the drain voltage, and the synchronous switch is turned on according to the gate control signal.

Abstract: A manufacturing method manufactures an electronic device, and includes the steps of: providing a first temporary panel including a first carrier board, a first substrate, a second substrate and a second carrier board arranged in sequence; providing a second temporary panel including a third carrier board, a third substrate, a fourth substrate and a fourth carrier board arranged in sequence; and removing the second carrier board and the third carrier board, and fixing the second substrate and the third substrate with an attaching member.

Abstract: A sticking machine able to automatically remove films on either side of a sheet to be pasted to a workpiece includes a sheet supply component, a sheet selection component, a drive component, a first film-removing component, a second film-removing component, a carrier, and a transmission line. The sheet supply component stores sheets. The sheet selection component applies suction to the sheet. The first film-removing component tears off a first film, the second film-removing component tears off a second film on the reverse side. The transmission line carries the workpiece to the carrier. The sticking machine is fed by the sheet supply component, and after removal of the first film, the sheet selection component lays the sheet on the surface of the workpiece, then the second film-removing component tears off the second film, realizing automatic sticking of the sheet on the workpiece, improving the processing efficiency and accuracy.

Abstract: An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

Abstract: A driving circuit, a driving method and a microfluidic substrate are provided. The driving circuit includes a first switching unit, a second switching unit, a reset unit, a first capacitor, and a second capacitor. In a first stage of a driving process of the driving circuit, the first switching unit is turned on, a first voltage signal is transmitted to a first node, the second switching unit is turned on, a second voltage signal is input to an output terminal of the driving circuit, and the driving circuit outputs an AC signal. In a second stage of the driving process, the first switching unit is turned off, the valid signal output by the second scan signal terminal controls the reset unit to be turned on, a third voltage signal is input to the output terminal of the driving circuit for reset, and the driving circuit outputs a DC signal.