Patents by Inventor Wei-An Lin
Wei-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250097013Abstract: The present disclosure relates to secure deployment of model weights from a generative artificial intelligence (GenAI) platform to a cloud service. The method includes accessing the model metadata and a set of weights of a GenAI model associated with a GenAI platform. These model weights may be encrypted using a first encryption key that may be provided in the model metadata. These encrypted model weights may be decrypted based on the model metadata by utilizing the first encryption key from the model metadata. Each key may be associated with the specific type of GenAI model. Before storing the model weights from the GenAI platform cloud tenancy to a cloud storage in GenAI home region, the model weights may be encrypted again by utilizing a second encryption key. This encryption by the cloud may enable independent control over the sensitive information during transit and storing.Type: ApplicationFiled: May 28, 2024Publication date: March 20, 2025Applicant: Oracle International CorporationInventors: Ming Fang, Simo Lin, Beiwen Guo, Wei Gao
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Publication number: 20250098378Abstract: A method for manufacturing an optoelectronic structure and a package structure are provided. The method includes providing a substrate and a light source module and a photonic component over the substrate; and adjusting a lens structure to a unit specific position related to the substrate to couple an optical signal from the light source module to the photonic component.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pei-Jung YANG, Jr-Wei LIN, Mei-Ju LU, Chi-Han CHEN
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Publication number: 20250098319Abstract: A display panel includes sub-pixels, first and second regions arranged along a first direction, and first side and second side. First sub-pixel groups in the first region and second sub-pixel groups in the second region are arranged along the first direction, and include at least two sub-pixels arranged along the second direction. A number of the sub-pixels in the second sub-pixel group close to the first region is greater than a number of the sub-pixels in the second sub-pixel groups away from the first region. The first sub-region of the second region is closer to the first region than the second sub-region. From the first region to the second region, a variation rate of the numbers of the sub-pixels in the second sub-pixel groups in the first sub-region is greater than a variation rate of the numbers of the sub-pixels in the second sub-pixel groups in the second sub-region.Type: ApplicationFiled: December 2, 2024Publication date: March 20, 2025Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.Inventors: Kunfeng ZHANG, Yiqiang LIN, Wei WU, Boping SHEN
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Publication number: 20250098116Abstract: A thermally conductive board includes a top metal layer, a bottom metal layer, and an electrically insulating but thermally conductive layer (for simplification hereinafter referred to as “thermally conductive layer”) laminated between the top metal layer and the bottom metal layer. The thermally conductive layer includes a polymer matrix and a thermally conductive filler dispersed in the polymer matrix. The polymer matrix includes an epoxy-based composition consisting of epoxy and chlorine-containing impurities. The chlorine content of the thermally conductive layer is lower than 300 ppm.Type: ApplicationFiled: February 15, 2024Publication date: March 20, 2025Inventors: KAI-WEI LO, Cheng Yi Lin, KUAN-YU CHEN
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Publication number: 20250096119Abstract: The present disclosure provides a resistive device. The resistive device includes a conductive structure, a row of first vias, and a row of second vias. The conductive structure has a first side and a second side opposite to the first side, and a first surface connected between the first side and the second side. The row of first vias extends through the conductive structure in a first direction substantially perpendicular to the first surface. The row of first vias is closer to the first side than the second side. The row of second vias extends through the conductive structure in the first direction. The row of second vias is disposed between the first side of the conductive structure and the row of first vias.Type: ApplicationFiled: September 14, 2023Publication date: March 20, 2025Inventors: WEI-LIN LAI, SZU-LIN LIU
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Publication number: 20250098238Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.Type: ApplicationFiled: October 23, 2023Publication date: March 20, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ting Chiang, Tien-Shan Hsu, Po-Chang Lin, Lung-En Kuo, Hao-Che Feng, Ping-Wei Huang
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Publication number: 20250096083Abstract: This disclosure provides a semiconductor package including a chip, a drain lead frame assembly, a source lead frame assembly, and an insulation layer. The chip includes an opposite drain surface and source surface. The drain lead frame assembly includes a drain contact plate, a drain connecting section, and drain leads integrally formed into one piece. The drain contact plate is physically connected to the drain surface. An area of the drain contact plate is larger than that of the drain surface. The source lead frame assembly includes a source contact plate, a source connecting section, and source leads integrally formed into one piece. The source contact plate is physically connected to the source surface. An area of the source contact plate is smaller than that of the source surface. The insulation layer encapsulates the chip and surrounds the drain contact plate and the source contact plate.Type: ApplicationFiled: November 26, 2023Publication date: March 20, 2025Inventors: Li-Zheng LIN, Lan-Wei WEN
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Publication number: 20250096808Abstract: A voltage-controlled oscillator includes an input circuit, a first current supply circuit, a second current supply circuit, a filtering circuit, and an oscillating circuit. The input circuit includes an operational amplifier and a first input transistor. The operational amplifier generates an output voltage according to an input voltage and a feedback voltage. The first input transistor generates an input current according to the output voltage and a power supply voltage. The first current supply circuit generates a first output current according to the input current. The second current supply circuit generates a second output current according to the input current. The filtering circuit couples to the input circuit and the second current supply circuit, and decrease an influence caused by a variation of the input current on the second current supply circuit. The oscillating circuit generates an output clock according to the first output current and the second output current.Type: ApplicationFiled: September 3, 2024Publication date: March 20, 2025Inventors: KUO-WEI WU, Yen-Ju Lin
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Publication number: 20250093593Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.Type: ApplicationFiled: January 3, 2024Publication date: March 20, 2025Inventors: Wen-Chih Lin, Cheng-Yu Kuo, Yen-Hung Chen, Hsuan-Ting Kuo, Chia-Shen Cheng, Chao-Wei Li, Ching-Hua Hsieh, Wen-Chih Chiou, Ming-Fa Chen, Shang-Yun Hou
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Publication number: 20250096071Abstract: Provided are integrated circuit systems and methods for fabricating semiconductor packages. An integrated circuit system includes a circuit board having a top side and a bottom side and defining an opening from the top side to the bottom side; a bottom boiling plate having a recessed portion and having a projection with a terminal surface, wherein the recessed portion is located below the bottom side of the circuit board, wherein the projection extends through the opening, and wherein the terminal surface is located above the top side of the circuit board; a semiconductor substrate located over the top side of the circuit board and including semiconductor devices; and a top boiling plate located over the semiconductor substrate, wherein the bottom boiling plate and the top boiling plate are configured to dissipate heat away from the integrated circuit system.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsunyen Wu, Po-Yao Lin, Sing-Da Jiang, Shih-Wei Liu, Kathy Yan
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Publication number: 20250094223Abstract: A system and computer-implemented method include receiving a request for allocating graphical processing unit (GPU) resources for performing an operation. The request includes metadata identifying a client identifier (ID) associated with a client, throughput, and latency of the operation. A resource limit is determined for performing the operation based on the metadata. Attributes associated with each GPU resource of a plurality of GPU resources available for assignment are obtained. The attribute is analyzed that is associated with each GPU resource with respect to the resource limit. A set of GPU resources is identified from the plurality of GPU resources based on the analysis. A dedicated AI cluster is generated by patching the set of GPU resources within a single cluster. The dedicated AI cluster reserves a portion of a computation capacity of a computing system for a period of time and the dedicated AI cluster is allocated to the client associated with the client ID.Type: ApplicationFiled: May 28, 2024Publication date: March 20, 2025Applicant: Oracle International CorporationInventors: Ming Fang, Simo Lin, Jinguo Zhang, Wei Gao
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Publication number: 20250094234Abstract: A system and computer-implemented method include accessing a request for allocating graphical processing unit (GPU) resources for performing an operation. The request includes metadata identifying a client identifier associated with a client, throughput, and a latency of the operation. A predicted resource limit for performing the operation is determined based on the metadata. A parameter of GPU resources is obtained. The parameter includes a status indicating whether a GPU resource is occupied for performing another operation. A GPU resource utilization value is determined for each node based on the status. The GPU resource utilization value indicates the amount of utilization of GPU resources of the corresponding node. The GPU resource utilization value of each node is compared with a pre-defined resource utilization threshold value. The GPU resources are re-scheduled based on the predicted resource limit. Further, a set of GPU resources from the re-scheduled GPU resources for performing the operation.Type: ApplicationFiled: May 28, 2024Publication date: March 20, 2025Applicant: Oracle International CorporationInventors: Ming Fang, Yifeng Liu, Simo Lin, Wei Gao
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Publication number: 20250095908Abstract: The network transformer includes an iron core body, and first, second, and third winding assemblies. The iron core body has first and second winding sections. A first flange and a second flange are on both ends of the iron core body, and a third flange situated between the first and second flanges. The first winding section is positioned between the first and third flange s, while the second winding section is located between the second and third flanges. The first, second, and third flanges respectively have first, second, and third electrode sets. The two ends of the coils in the first winding assembly are electrically connected to the first electrode set. The second winding assembly has the two ends of the coils electrically connected to the third electrode set. The third winding assembly has the two ends of the coils electrically connected to the second and third electrode sets.Type: ApplicationFiled: September 14, 2023Publication date: March 20, 2025Inventors: Ming-Yen Hsieh, Pao-Lin Shen, Hsiang-Chung Yang, Wei-Hsuan Lo
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Publication number: 20250096460Abstract: An adjustable antenna array and an electronic apparatus are provided. The adjustable antenna array includes: a first substrate and a second substrate opposite to each other, and antenna sub-arrays in an array. Each of at least some antenna sub-arrays includes a phase shifter, a power division feeding network, and a plurality of radiating units. The phase shifter and the power division feeding network are between the first substrate and the second substrate. At least some radiating units are connected to the phase shifter through the power division feeding network. Antenna patterns corresponding to the plurality of radiating units at least include patterns on a side of the second substrate away from the first substrate. An area of an orthographic projection of the power division feeding network on the first substrate is smaller than an area of an orthographic projection of the phase shifter on the first substrate.Type: ApplicationFiled: August 26, 2022Publication date: March 20, 2025Inventors: Lu CHEN, Xiaoqiang YANG, Yiming WANG, Zixiang LIN, Wei ZHAO, Cuiwei TANG, Zhifeng ZHANG
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Patent number: 12255236Abstract: Field effect transistors and method of making. The field effect transistor includes a pair of active regions over a channel layer, a channel region formed in the channel layer and located between the pair of active regions, and a pair of contact via structures electrically connected to the pair of active regions. The contact via structure is formed in an interlayer dielectric layer that extends over the channel layer.Type: GrantFiled: August 9, 2023Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hung Wei Li, Mauricio Manfrini, Sai-Hooi Yeong, Yu-Ming Lin
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Patent number: 12254426Abstract: A production line operation forecast method and a production line operation forecast system are provided. The production line operation forecast method includes the following steps: obtaining an online production line work-in-process map at a time point, generating candidate simulated dispatch decisions based on the online production line work-in-process map, and inferring production-line work-in-process map changes of the candidate simulated dispatch decisions at a next time point; inputting the production-line work-in-process map changes to a forecast model, such that the forecast model outputs simulated production line operation health indicators of the candidate simulated dispatch decisions at the next time point; and selecting one of the candidate simulated dispatch decisions as a scheduling dispatch decision.Type: GrantFiled: July 27, 2022Date of Patent: March 18, 2025Assignee: Industrial Technology Research InstituteInventors: Tsan-Cheng Su, Hao-Jhe Huang, Chung-Wei Lin
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Patent number: 12254815Abstract: A method for reducing a color edge phenomenon of a display panel is provided. The method is applicable to a display panel including a plurality of pixel units. The method includes: performing pixel adjustment on the pixel units at edges of the display panel. Each pixel unit includes at least three sub-pixels: a first sub-pixel, a second sub-pixel, and a third sub-pixel. By adjusting positions, areas, or brightness of the sub-pixels, the color edge phenomenon of the display panel is effectively reduced or avoided.Type: GrantFiled: November 2, 2023Date of Patent: March 18, 2025Assignee: ASUSTEK COMPUTER INC.Inventors: Chen-Wei Lin, Chin-An Tseng, Yung-Ming Huang
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Patent number: 12254594Abstract: Methods, systems, and non-transitory computer readable media are disclosed for intelligently enhancing details in edited images. The disclosed system iteratively updates residual detail latent code for segments in edited images where detail has been lost through the editing process. More particularly, the disclosed system enhances an edited segment in an edited image based on details in a detailed segment of an image. Additionally, the disclosed system may utilize a detail neural network encoder to project the detailed segment and a corresponding segment of the edited image into a residual detail latent code. In some embodiments, the disclosed system generates a refined edited image based on the residual detail latent code and a latent vector of the edited image.Type: GrantFiled: April 1, 2022Date of Patent: March 18, 2025Assignee: Adobe Inc.Inventors: Hui Qu, Jingwan Lu, Saeid Motiian, Shabnam Ghadar, Wei-An Lin, Elya Shechtman
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Patent number: 12253489Abstract: A gas sensor includes a first electrode, a gas detecting layer disposed on the first electrode, and an electric-conduction enhanced electrode unit being electrically connected to the first electrode and the gas detecting layer. The electric-conduction enhanced electrode unit includes an electric-conduction enhancing layer and a second electrode electrically connected to the electric-conduction enhancing layer. The electric-conduction enhancing layer is electrically connected to the gas detecting layer and is made of an electrically conductive organic material.Type: GrantFiled: October 28, 2022Date of Patent: March 18, 2025Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Hsiao-Wen Zan, Hsin-Fei Meng, Yu-Chi Lin, Shang-Yu Yu, Ting-Wei Tung, Yi-Chu Wu, Yu-Nung Mao
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Patent number: 12252777Abstract: A physical vapor deposition (PVD) system is provided. The PVD system includes a PVD chamber defining a PVD volume within which a target material of a target is deposited onto a wafer. The PVD system includes the target in the PVD chamber. The target is configured to overlie the wafer. An edge of the target extends from a first surface of the target to a second surface of the target, opposite the first surface of the target. A first portion of the edge of the target has a first surface roughness. The first portion of the edge of the target extends at most about 6 millimeters from the first surface of the target to a second portion of the edge of the target. The second portion of the edge of the target has a second surface roughness less than the first surface roughness.Type: GrantFiled: May 7, 2021Date of Patent: March 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Sheng-Ying Wu, Ming-Hsien Lin, Po-Wei Wang, Hsiao-Feng Lu