Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: In an embodiment of the techniques presented herein, a charging system includes an input port, a wireless charging unit, having a magnetic charging interface, and a wireless charging controller configured to generate a magnetic charging signal at the magnetic charging interface based on a first connection state of the magnetic charging interface, and a universal serial bus power delivery (USB-PD) power adaptor, having an output port, and a USB-PD controller configured to deliver power to the output port, wherein a first portion of available power at the input port is allocated to the wireless charging unit for generating the magnetic charging signal responsive to the first connection state indicating a connected device, and a second portion of the available power at the input port is allocated to the USB-PD adaptor based on the first portion allocated to the wireless charging unit.

Abstract: A package substrate includes a core layer, at least one functional component, at least one spacer, a filler, a first and a second build-up structures. The core layer has at least one opening and multiple conductive through vias. The functional component is disposed in the openings. The spacer is disposed on the functional component. The filler is filled in the opening, covering the functional component and spacer, and completely filling the gap between the opening, the functional component and the spacer. The first build-up structure is disposed on a first surface of the core layer and a third surface of the filler, and electrically connected to the functional component and the conductive through vias. The second build-up structure is disposed on a second surface of the core layer and a fourth surface of the filler, contacts the spacer and electrically connected to the conductive through vias.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain (S/D) portion adjacent to the gate electrode, and an interlayer dielectric layer adjacent formed over the source/drain portion. The semiconductor device structure includes an etch stop layer adjacent between the source/drain portion and the interlayer dielectric layer, and a protective element adjacent formed over the interlayer dielectric layer.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: Techniques for facilitating natural language interactions with visual interactive content are described. During a build time, a system analyzes various websites and applications relating to a particular user goal to understand website and application navigation and information relating to the user goal. The learned information is used to store configuration data. During runtime, when a user request performance of an action, the system engages in a dialog with the user to complete the user's goal. The system uses the stored configuration data to determine actions to be performed at a website or application to complete the user's goal, and determines system responses to present to the user to facilitate completion of the goal. Such system responses may request information from the user, may inform the user of information displayed at the website or application, etc.

Abstract: Error alert encoding for improved error mitigation is described. In one or more implementations, a system includes a processor configured to receive an encoded signal indicating a type of an error detected in a memory, and output one or more mitigation commands to mitigate the type of the error detected in the memory based on the encoded signal. In one or more implementations, a memory system includes a memory and a buffer. The buffer is configured to output an encoded signal indicating a type of an error detected in the memory.

Abstract: A semiconductor package and the method of forming the same are provided. The semiconductor package may include a substrate, a semiconductor package component having a semiconductor die bonded to the substrate, a lid attached to the substrate, and a first composite metal feature between the semiconductor package component and the lid. The first composite metal feature may include a first metal feature having a first material and a second metal feature having a second material. The first material may be an intermetallic compound. The second material may be different from the first material.

Abstract: The present disclosure relates to a backlight module and a display device. The backlight module includes a lamp panel including a first surface and a second surface opposite to each other, wherein the first surface comprises a light source array, a first back plate connected with the lamp panel at a side of the second surface of the lamp panel, a second back plate connected with the first back plate at a side of the first back plate away from the lamp panel, an optical film layer located on the first surface of the lamp panel; at least one light-transmitting support column comprising a base portion and a protrusion portion located on an upper surface of the base portion, the protrusion portion passing through the lamp panel and protruding from a side of the first surface of the lamp panel to support the optical film layer.

Abstract: A package structure includes a frontside redistribution layer (RDL) structure with a recessed portion, a lower encapsulation layer on the frontside RDL structure and a plurality of through vias connected to the frontside RDL structure to an upper package, a first semiconductor die on the frontside RDL structure and in the lower encapsulation layer, and an integrated passive device (IPD) connected to the frontside RDL structure in the recessed portion that connects to the first semiconductor die. A method of forming a package structure includes forming a molded portion with a lower encapsulation layer, a plurality of through vias in the lower encapsulation layer and a first semiconductor die in the lower encapsulation layer, forming a RDL structure with a recessed portion on the molded portion, the plurality of through vias connect the frontside RDL structure to an upper package, and attaching an IPD in the recessed portion.

Abstract: An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit of the clock skew calibration circuit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal, a frequency divider configured to receive the clock signal and generate a reduced frequency signal indicative of a skew of a first multi-phase clock signal, and a delay line control circuit configured to adjust the skew of the first multi-phase clock signal by comparing the reduced frequency signal with a predetermined duty cycle, and generating a control signal to modify a delay applied to the first multi-phase clock signal.

Abstract: An evaporation mask includes an outer frame and a sub-mask. The outer frame is provided with an opening, and both sides of the opening are provided with two opposite positioning side edges. The sub-mask is adapted to be connected to the outer frame and is provided with a pattern area and two fixed areas. The pattern area is located at a center of the sub-mask. A surface of the sub-mask is provided with a first datum point and a second datum point. The first datum point is located at a center of the pattern area. The second datum point is located at an edge, close to one of the fixed areas, of the pattern area. A first distance between the first datum point and the second datum point is less than or equal to 200 ?m. A method for evaluating the evaporation mask is also provided.

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a photonic integrated circuit component, an electric integrated circuit component, a lens and an optical signal port. The photonic integrated circuit component comprises an optical input/output portion configured to transmit and receive optical signal. The electric integrated circuit component is electrically connected to the photonic integrated circuit component. The lens is disposed on a sidewall of the photonic integrated circuit component. The optical signal port is optically coupled to the optical input/output portion.

Abstract: A method of performing code review and a code review system are provided. The code review system includes a code repository, a static scanning tool, an analytical neural network and a generative neural network. The code repository is configured to store an original source code and a new code created by a developer in response to a code change request to merge the new code with the original source code. The static scanning tool is configured to collect data associated with each commit in the new code. The analytical neural network is implemented with an analytical AI and configured to assess a risk level of each commit in the new code. The generative neural network is implemented with a generative AI and configured to provide a code summarization and an initial code review comment of each commit in the new code.

Abstract: In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.

Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.

Abstract: A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Abstract: A Totem Pole PFC circuit includes at least one fast-switching leg, a slow-switching leg, and a control unit. Each fast-switching leg includes a fast-switching upper switch and a fast-switching lower switch. The slow-switching leg is coupled in parallel to the at least one fast-switching leg, and the slow-switching leg includes a slow-switching upper switch and a slow-switching lower switch. The control unit receives an AC voltage with a phase angle, and the control unit includes a current detection loop, a voltage detection loop, and a control loop. The control loop generates a second control signal assembly to respectively control the slow-switching upper switch and the slow-switching lower switch. The control loop controls the second control signal assembly to follow the phase angle, and dynamically adjusts a duty cycle of the second control signal assembly to turn on or turn off the slow-switching upper switch and the slow-switching lower switch.