Abstract: Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.

Abstract: A forward converter includes a voltage conversion device, a switch and an auxiliary device. The voltage conversion device includes a primary winding and a secondary winding, and is configured to convert an input voltage into an output voltage. The switch is connected to the voltage conversion device, and is switched to make the voltage conversion device receive or not receive the input voltage. The auxiliary device is connected to the voltage conversion device. When the switch is cut off, the auxiliary device stores electrical energy released by the voltage conversion device and generates a compensation voltage, and when the switch is turned on, the auxiliary device provides the compensation voltage, wherein the compensation voltage and the input voltage have same polarity. The present disclosure further provides a forward power factor corrector including the forward converter described above and a rectifying device.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Abstract: A broadband dual-feed circularly-polarized antenna includes first, second and third substrate modules. The first substrate module includes a parasitic element, and a radiator disposed below the parasitic element. The second substrate module is stacked below the first substrate module, and is provided with first and second slots. The third substrate module is stacked below the second substrate module, and includes first and second feed lines. When the antenna operates in a transmit mode, signals fed to the first and second feed lines are electromagnetically coupled to the first and second slots, then to the radiator, and finally to the parasitic element, and the parasitic element transmits an electromagnetic wave. When the antenna operates in a receive mode, the parasitic element receives an electromagnetic wave, and the electromagnetic wave is electromagnetically coupled to the radiator, then to the first and second slots, and finally to the first and second feed lines.

Abstract: A system for analysing an image of a body part, the system including: an extractor module for extracting image features from the image; a transformer, including: an encoder including multiple encoder layers, and a decoder including multiple decoder layers, wherein each layer of the encoder and decoder includes a bi-linear multi-head attention layer configured to compute second-order interactions between vectors associated with the extracted image features; and a positional encoder configured to provide contextual order to an output of the bi-linear multi-head attention layer of the decoder; and a text-generation module to generate a text-based medical report of the image based on an output from the transformer.

Abstract: A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

Abstract: Fluid collection systems having a canister, a lid, and a liner assembly are described. The liner assembly may include a liner and a fitment assembly. The fitment assembly may be connected to the liner by a gland. The fitment assembly may be held in place by at least one of any number of features, including a bracket or other fitment support connected to the canister and/or the lid, supports integrated into the fitment itself, a snapping mechanism, or a notch in one or more of the canister and the lid that supports the fitment.

Abstract: A display includes a first light emitting device. The first light emitting device includes a first switch and a second switch. The first switch is configured to adjust a first node according to a first clock signal. The second switch is configured to generate a first light emitting signal according to a first voltage signal. A control end of the second switch is coupled to the first node. The first clock signal switches between a first voltage level and a second voltage level. The first voltage signal has a third voltage level. The third voltage level is more than one of the first voltage level and the second voltage level and is less than the other one of the first voltage level and the second voltage level.

Abstract: A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.

Abstract: A hotel demand evaluation method includes setting a plurality of keywords, collecting a plurality of texts according to the plurality of keywords, selecting a plurality of valid texts from the plurality of texts, performing a semantic analysis operation to identify at least one time keyword and at least one location keyword in the plurality of valid texts, generating a classification result according to at least the at least one time keyword and the at least one location keyword, classifying each valid text of the plurality of valid texts into a positive impact group, a no impact group or a negative impact group according to the classification result, and generating a hotel demand score of a specific region according to at least one valid text of the positive impact group and/or at least one valid text of the negative impact group.

Abstract: A metal mask includes a metal plate having an evaporation surface and a back surface and a plurality of through-holes. Each through-hole forms a first opening on the evaporation surface and a neck opening between the evaporation surface and the back surface. The first opening has two first long edges and two opposite first short edges. The neck opening has two second long edges and two second short edges. A ratio of a length of the second long edge to a length of the second short edge is equal to or greater than 2.5. A first angle is formed between a connecting line between the first long edge and the second long edge and the back surface, a second angle is formed between a connecting line between the adjacent first short edge and second short edge and the back surface, and the second angle is less than the first angle.

Abstract: A manufacturing method of a resin composition includes the following steps. An inorganic filler, a first solvent, and a dispersant are mixed, wherein a material of the dispersant is silane and/or polysiloxane including an organic-philic end and an inorganic-philic end, and the dispersant and the inorganic filler undergo a dealcoholization condensation reaction reaction to form a dispersion including a modified inorganic filler. The organic-philic end includes a carbonyl group, an epoxy group, and/or an amine group. Epoxy resin is dissolved into the dispersion.

Abstract: An imaging lens assembly module includes an imaging lens element set, a light folding element and a plate-shaped light blocking element. The imaging lens element set has an optical axis, and includes a lens element. The light folding element is configured to fold the optical axis at least once, and includes an incident surface, an exit surface and an optical reflecting surface. The plate-shaped light blocking element keeps an air distance between the plate-shaped light blocking element and the light folding element, and includes two layered structures and columnar air structures. The layered structures are corresponding to the light folding element. The columnar air structures are farther away from the light folding element than a surface of the plate-shaped light blocking element from the light folding element, and the surface of the plate-shaped light blocking element faces toward the light folding element.

Abstract: Systems and structures for venting and flow conditioning operations in charged particle beam systems. In some embodiments, a system may include a chamber configured to provide a vacuum environment; a vent valve; and a mass flow controller coupled to the chamber on a first side of the mass flow controller and to the vent valve on a second side of the mass flow controller.

Abstract: A wearable device includes a host and a head strap module. The host has a pair of host connecting ends. The head strap module includes a head strap body and a pair of strengthening assemblies. The head strap body has a pair of head strap connecting ends. The pair of head strap connecting ends are respectively detachably assembled to the pair of host connecting ends. Each of the pair of strengthening assemblies has an outer cover and an inner cover. The outer cover and the corresponding inner cover are connected to each other to jointly cover and hold the corresponding host connecting end and the corresponding head strap connecting end. In addition, a head strap module applied to a wearable device is also provided.

Abstract: A computer peripheral device is provided. The computer peripheral device is adapted to be installed in an electronic device supporting signal transmission of a first signal frequency. The computer peripheral device includes a human interface device (HID) and a bridging device. The HID includes a control unit to support signal transmission of a second signal frequency. The bridging device includes a first universal serial bus (USB) interface unit and a second USB interface unit. The first USB interface unit is adapted to be electrically connected to the electronic device, and supports signal transmission of the first signal frequency. The second USB interface unit is adapted to be electrically connected to the HID. The second USB interface unit regards the HID as a communication device class (CDC) device, instructs the control unit to generate an input signal at a timing corresponding to the first signal frequency, and transmits the input signal to the electronic device.

Abstract: A method is provided. The method includes detaching an upper shell of a reticle pod from a base. The method further includes while the upper shell is detached from the base, blocking an inlet flow of gas from entering an interior of the reticle pod between the upper shell and the base with a use of a fluid regulating module which is in a sealed state. In the sealed state of the fluid regulating module, an opening of the fluid regulating module is covered with a sealing film. The method also includes removing a reticle positioned on the base to a process tool. In addition, the method includes performing a lithography operation in the process tool with the use of the reticle.

Abstract: The present disclosure provides an interspinous process device. The interspinous process device may include a main body having a cavity formed therein, the main body being configured to be disposed between the two adjacent spinous processes; and a spacer configured to be arranged in the cavity of the main body. When the main body is disposed between the two adjacent spinous processes and the spacer is arranged in the cavity of the main body, a volume of the cavity may be greater than a volume of the spacer, a height of the cavity may be equal to a height of the spacer, and a width of the cavity may be greater than a width of the spacer.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.