Patents by Inventor Wei An

Wei An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240192387
    Abstract: The present disclosure provides a radiation detector, including a substrate, a pixel array formed on the substrate, a perovskite thick film formed on the pixel array and having a cubic crystal phase, a first electrode formed on the perovskite thick film and is opposite to the pixel array, and a readout circuit. The radiation detector has significantly reduced dark current density and high sensing sensitivity. The present disclosure also provides a method for preparing the perovskite thick film.
    Type: Application
    Filed: December 29, 2022
    Publication date: June 13, 2024
    Inventors: Kuo-Wei HUANG, Jen-An CHEN, Yung-Liang TUNG
  • Publication number: 20240188866
    Abstract: An early assistive diagnosis system of ADHD provides a test to the subject and uses a brain-computer interface (BCI) to detect the electroencephalography (EEG) signals of subject. A host receives the EEG signals, captures the features associated with ADHD heterogeneities, obtains feature EEG signals, and classifies the subject as typical development or ADHD, then uses the EEG feature signals to train a predicted index score range for the heterogeneities of ADHD. The test scores of a new subject is tested, it is compared whether the scores fall within the predicted index score range to determine the ADHD heterogeneity types to which the new subject belongs. Thus, the present invention uses attention tests for ADHD in combination with EEG signals to assess symptoms of a subject, further predicts the potential aptitude of a subject for ADHD and provides objective assistive diagnosis to physicians.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 13, 2024
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Li-Wei KO, I-Chun CHEN, I-Wen HUANG, Jo-Wei LIN, Zuo-Cian FAN, Chih-Hao CHANG, Yang CHANG
  • Publication number: 20240196390
    Abstract: PUCCH carrier switching at a UE may include decoding an RRC configuration including a time-domain pattern indicating a reference cell and a target PUCCH cell for one or more PUCCH transmissions at a given point in time. The reference cell may include a reference cell slot numerology and the target PUCCH cell may include a target PUCCH cell slot numerology. A slot for PUCCH transmissions may be determined based on the reference cell slot numerology. The determined slot may be used for transmission of at least one of an SR, a CSI, and a HARQ-ACK. The determined slot of the reference cell may be mapped to a corresponding slot of the target PUCCH cell. A PUCCH resource may be determined for performing a PUCCH transmission using the corresponding slot of the target PUCCH cell. The PUCCH resource determination may be based on a PUCCH configuration of the target PUCCH cell.
    Type: Application
    Filed: September 24, 2021
    Publication date: June 13, 2024
    Inventors: Sigen Ye, Chunhai Yao, Chunxuan Ye, Dawei Zhang, Haitong Sun, Hong He, Seyed Ali Akbar Fakoorian, Wei Zeng, Weidong Yang, Yushu Zhang
  • Publication number: 20240194260
    Abstract: A method for forming a 3D memory device includes forming an array wafer having a memory array layer and a CMOS layer stacked together, including: forming the CMOS layer having HV circuitry of a plurality of peripheral devices, and forming a plurality of memory cells and a string structure in the memory array layer. The memory array layer includes at least one cell region for forming the memory cells and at least one string structure region for forming the string structure, and the CMOS layer includes at least one string driver region. The method also includes forming a CMOS wafer having LV circuitry and LLV circuitry of the plurality of peripheral devices, the CMOS wafer including at least one page buffer region; bonding the array wafer and the CMOS wafer at a bonding interface; and forming the 3D memory device based on the bonded array wafer and CMOS wafer.
    Type: Application
    Filed: December 28, 2022
    Publication date: June 13, 2024
    Inventors: Liang CHEN, Wei LIU
  • Publication number: 20240196364
    Abstract: The present disclosure provides a method and apparatus for distinguishing paging capability of a base station, and a communication device, belonging to the technical field of wireless communication. The method includes: a terminal device receives paging signaling of a base station, and acquires a paging capability indication message in the paging signaling, where the paging capability indication message is used to carry a paging cause.
    Type: Application
    Filed: April 13, 2021
    Publication date: June 13, 2024
    Applicant: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
    Inventor: Wei HONG
  • Publication number: 20240192256
    Abstract: The present invention disclosed a method for calculating an oscillation damping ratio of a power grid, and relates to the field of power system operation and control. When a power system oscillates, an oscillation period, two oscillation extreme points, and an oscillation direct current component start to be detected. Then an oscillation decay time constant is calculated according to the two oscillation extreme points and the oscillation direct current component. The oscillation damping ratio is calculated through the oscillation decay time constant and the oscillation period. Compared with a conventional fitting method, the conventional fitting method cannot calculate and analyze the oscillation damping ratio in a cast that a complete oscillation waveform is not obtained. The method proposed by the present inventive patent may complete the calculation of the oscillation damping ratio in a case of obtaining 2 pieces of data, so as to accelerate the speed of calculation.
    Type: Application
    Filed: February 23, 2024
    Publication date: June 13, 2024
    Inventors: Yihui ZHANG, Libin WEN, Guangshi LIU, Qian DOU, Dongshan HUANG, Xiaoming WANG, Zhiyuan SUN, Guangling LU, Mingpo LI, Mosi LIU, Hao QIU, Xiaoyin QIU, Zhiyang YAO, Wei ZHANG
  • Publication number: 20240194295
    Abstract: In certain aspects, provided herein are methods and systems for methylation quantification based on a Cellular Het-crogeneity-Adjusted cLonal Methylation (CHALM) quantification methodology described herein. Disclosed herein, in some aspects, are methods for identifying the methylation status of a biomarker in a single cell. In certain aspects, provided herein are methods for generating a methylation profile of a biomarker associated with a tumor species.
    Type: Application
    Filed: April 21, 2022
    Publication date: June 13, 2024
    Inventors: Wei LI, Jianfeng XU, David J. TAGGART
  • Publication number: 20240196715
    Abstract: Provided are a display panel and a display apparatus. The display panel includes a pixel definition layer on a first base substrate and including first barriers and second barriers, the first and second barriers defining first accommodating portions; light emitting devices arranged in first accommodating portions in a one-to-one correspondence; a first encapsulation layer covering the pixel definition layer and the light emitting devices; a color conversion layer on a side of the first encapsulation layer away from the first base substrate, and including light emergent portions; and a first light shielding pattern between the first encapsulation layer and the color conversion layer and including first light shielding strips extending in a first direction and second light shielding strips extending in a second direction.
    Type: Application
    Filed: September 2, 2021
    Publication date: June 13, 2024
    Inventors: Yang LI, Wei HUANG, Dejiang ZHAO, Tianhao LU, Yu TIAN, Qian JIN, Qian SUN
  • Publication number: 20240192091
    Abstract: A vehicle chassis health evaluation method and apparatus is disclosed. The method for health evaluation of vehicle chassis may include monitoring the vibration of at least one of the wheel end and the reducer by a vibration sensor. The vibration sensor is installed in the wheel end and/or the reducer. The method may further include, based on the monitored vibration of at least one of the wheel end and the reducer, performing the health evaluation of the vehicle chassis. The health evaluation method of the vehicle chassis of the present disclosure allows the real-time state of the vehicle chassis to be determined, even when the vehicle is driving, and critical safety accidents caused by the chassis can be avoided.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 13, 2024
    Inventors: Xing Yi, Yuanbing Yao, Jim Wei, Sumeng Lian
  • Publication number: 20240196621
    Abstract: A semiconductor device includes a base and a stack structure. The base includes a first surface defining at least one memory plane region. The stack structure is disposed on the first surface, and includes a first portion located at the edge of the memory plane region and a second portion different from the first portion. The first portion includes first contact structures penetrating through the stack structure in a first direction and extending to the base. The second portion includes second contact structures electrically connected with corresponding gate conductor layers in the stack structure. A top surface of the first contact structure away from the base is flush with a top surface of the second contact structure away from the base.
    Type: Application
    Filed: December 30, 2022
    Publication date: June 13, 2024
    Inventors: Zongliang Huo, Lei Xue, Wenbin Zhou, Wei Xu, Yanwei Shi, Zhengliang Xia, Han Yang, Xinwei Zou, Zhaohui Tang, Jiaji Wu, Cheng Chen
  • Publication number: 20240196372
    Abstract: The present disclosure provides a method, a communication device and a non-transitory computer storage medium for distinguishing paging capability of a base station, and a communication device, belonging to the technical field of wireless communication. The method includes: a terminal device receives paging signaling of a base station, and acquires a paging cause information element in the paging signaling, where the paging cause information element is used to carry a paging cause. In such a way, even if the base station does not send the paging cause to the terminal device, the terminal device can still determine the paging capability of the base station according to the paging cause information element, so as to perform subsequent actions or corresponding determinations according to the paging capability of the base station.
    Type: Application
    Filed: April 13, 2021
    Publication date: June 13, 2024
    Applicant: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
    Inventor: Wei HONG
  • Publication number: 20240188858
    Abstract: The invention provides a sidelight-type non-invasive glucose monitoring module, which includes a substrate, an sidelight-type light source assembly, an sidelight-type light sensing assembly and a blocking member. The sidelight-type light source assembly is arranged on the substrate and includes a light-emitting element and a first light-guiding element. The sidelight-type light sensing assembly is arranged on the substrate and includes a light-sensing element and a second light-guiding element. The blocking member is arranged between the sidelight-type light source assembly and the sidelight-type light sensing assembly to block the sidelight-type light source assembly from the sidelight-type light sensing assembly.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 13, 2024
    Inventors: Hsiu-Jung HUANG, Sheng-Wei CHEN
  • Publication number: 20240195771
    Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums which provide for sidebar communication threads forked from, or related to, a principal thread. Messages in the sidebar communication thread may include a history of the principal thread, including one or more messages from the principal thread, and may include a proposed principal thread message that is the subject of the sidebar thread discussion. The sidebar thread may also include sidebar thread messages that carries the conversation of the sidebar thread participants. Once a termination condition is reached for the sidebar thread, the sidebar thread terminates and either the proposed principal thread message (as potentially modified by participants of the sidebar thread) becomes an accepted principal thread message and it is posted to the principal thread as if it was sent by the sidebar initiator or no message is posted (e.g., the proposed principal thread message is rejected).
    Type: Application
    Filed: February 16, 2024
    Publication date: June 13, 2024
    Inventors: Amer Aref HASSAN, Wei-Chen CHEN
  • Publication number: 20240193605
    Abstract: Embodiments of this specification disclose a payment information processing method, apparatus, and device, and a medium. The solution can include: obtaining a payment request that is sent by a target organization and that is generated based on a payment operation performed by a user, where the payment request includes identification information of an authorized payment account; determining account status information of the authorized payment account; determining, based on the account status information, whether a transaction corresponding to the payment request is at a transaction risk, to obtain a first determining result; and if the first determining result indicates that the transaction is not at a transaction risk, performing a first payment procedure; or if the first determining result indicates that the transaction is at a transaction risk, performing a second payment procedure including a first identity verification process.
    Type: Application
    Filed: April 8, 2022
    Publication date: June 13, 2024
    Inventors: Hui Chen, Can Ma, Zhengming Shen, Wei Liao
  • Publication number: 20240192692
    Abstract: A heading and attitude correction method and a heading and attitude correction system are provided. The method includes: obtaining attitude data in a period of time; performing a linear regression analysis on the attitude data and time points in the time period to obtain a regression line and a standard deviation; obtaining a deviation value between the attitude data and the regression line at each of the time points; excluding the attitude data for which the deviation value is greater than or equal to at least twice the standard deviation; grouping the attitude data according to a grouping value to form clusters; comparing a total quantity of the attitude data in each of the clusters, and defining one of the clusters with a largest total quantity as an ideal cluster; and calculating an average of the attitude data in the ideal cluster as a reasonable attitude data.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 13, 2024
    Inventors: YUNG-TAI HSU, CHUN-HENG CHAO, YEN-WEI WANG, BO-YU ZHU
  • Publication number: 20240195573
    Abstract: Methods and apparatuses for separate indication of DL TCI state and UL TCI state are disclosed. A method comprises receiving an MAC CE updating the mapping of multiple TCI codepoints and associated TCI state(s), wherein, each TCI codepoint is associated with one UL TCI state or one DL TCI state or both one DL TCI state and one UL TCI state.
    Type: Application
    Filed: April 9, 2021
    Publication date: June 13, 2024
    Applicant: Lenovo (Beijing) Limited
    Inventors: Bingchao Liu, Chenxi Zhu, Wei Ling, Yi Zhang, Lingling Xiao
  • Publication number: 20240194537
    Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate in the second region, and a second epitaxial feature over the second fin. The isolation feature includes a first portion disposed on sidewalls of the first fin, a second portion disposed on sidewalls of the second fin, and a third portion located between the first fin and the second fin. The third portion has a thickness larger than the first portion and the second portion.
    Type: Application
    Filed: February 19, 2024
    Publication date: June 13, 2024
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20240194523
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect dielectric layer over a substrate. An interconnect via is within the interconnect dielectric layer, and an interconnect wire is over the interconnect via and within the interconnect dielectric layer. A protective layer surrounds the interconnect via. The interconnect via vertically extends through the protective layer to below a bottom of the protective layer. The protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao
  • Publication number: 20240194441
    Abstract: The present disclosure provides a power adjustment method of an upper electrode power supply of a semiconductor process apparatus. The method includes obtaining a processing load of an upper electrode power supply of a reference process chamber and a processing load of an upper electrode power supply of a current process chamber corresponding to semiconductor process step, when starting to perform a semiconductor process step, determining a power compensation coefficient for the current process chamber relative to the reference process chamber based on the processing load of the current process chamber and the processing load the reference process chamber, and controlling the upper electrode power supply to output compensation power. The compensation power is a product of the set power of the upper electrode power supply of the current process chamber corresponding to the semiconductor process step and the corresponding power compensation coefficient.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 13, 2024
    Inventors: Jing WEI, Yu ZHANG, Gang WEI, Jing YANG, Guibin WANG, Xin YUE
  • Publication number: 20240191123
    Abstract: Provided a heat storage graphite having a low degree of orientation, a composition for preparing heat storage graphite having a low degree of orientation, and a method for preparing heat storage graphite having a low degree of orientation. The heat storage graphite comprises, in terms of the total mass of the heat storage graphite, 65-85 wt % of dispersed-phase graphite and 15-35 wt % of continuous-phase graphite, wherein the dispersed-phase graphite is spherical graphite, and the sphericity of the spherical graphite is 0.5-1; the ratio of the vertical thermal conductivity/plane-oriented thermal conductivity of the heat storage graphite is 0.4-0.8; and the plane-oriented thermal conductivity of the heat storage graphite is 50-150 W/mK. The heat storage graphite has the advantages of a low degree of orientation and high plane-oriented thermal conductivity.
    Type: Application
    Filed: November 26, 2021
    Publication date: June 13, 2024
    Applicants: CHINA ENERGY INVESTMENT CORPORATION LIMITED, NATIONAL INSTITUTE OF CLEAN-AND-LOW-CARBON ENERGY
    Inventors: Chunting DUAN, Chang WEI, Wenbin LIANG, Junqing LIU, Dongfang ZHENG, Guanghui GAO, Ying SHENG, Chengyu WEN