Abstract: Implementations of the present specification provide a method and an apparatus for managing a TLB cache in a virtualization platform, where the virtualization platform runs a plurality of virtual machines, each virtual machine is allocated with a unique VPID, and all virtual logical processors in the virtual machine share the VPID; and a guest process running in the virtual machine is allocated with a PCID. An identifier field of a TLB entry in the TLB cache includes a VPID and a PCID.

Abstract: Implementations of the present specification provide a method and an apparatus for managing a TLB cache in a virtualization platform, where the virtualization platform runs a plurality of virtual machines, each virtual machine is allocated with a unique VPID, and all virtual logical processors in the virtual machine share the VPID; and a guest process running in the virtual machine is allocated with a PCID. An identifier field of a TLB entry in the TLB cache includes a VPID and a PCID.

Abstract: A method and apparatus for controlling a neutral point clamped inverter circuit, and a neutral point clamped inverter. It is detected that whether the inverter circuit operates in an abnormal state. In a case that the inverter circuit operates in the abnormal state, a control mode of the inverter circuit is changed to a specified control mode in which a transistor that may be damaged is in an off state. In this way, there is not current flowing through the transistor, avoiding damage of the transistor and thereby improving safety of the inverter circuit.

Abstract: A method and apparatus for controlling an inverter circuit, and an inverter. It is detected that whether the inverter circuit operates in an abnormal state. In a case that the inverter circuit operates in the abnormal state, a control mode of the inverter circuit is changed to a specified control mode in which a transistor that may be damaged is in an off state. In this way, there is not current flowing through the transistor, avoiding damage of the transistor and thereby improving safety of the inverter circuit.

Abstract: A five-level inverter and its application circuit are provided. The five-level inverter is enabled to output multiple levels of voltage by controlling different conduction combinations of first, second, third, fourth, fifth, sixth, seventh, and eighth switch transistors, as well as a clamping capacitor. Two conduction combinations may be selected for outputting a positive voltage, with currents flowing through the clamping capacitor in opposite directions in the two conduction combinations. Therefore the voltage of the clamping capacitor can be balanced by controlling the two conduction combinations. Similarly, when outputting a negative voltage, the voltage of the clamping capacitor can be balanced by controlling other two conduction combinations. Therefore, a balance of power capacitor voltage can be achieved at full power and full modulation without adding an extra hardware circuit.

Abstract: A five-level inverter and its application circuit are provided. The five-level inverter is enabled to output multiple levels of voltage by controlling different conduction combinations of first, second, third, fourth, fifth, sixth, seventh, and eighth switch transistors, as well as a clamping capacitor. Two conduction combinations may be selected for outputting a positive voltage, with currents flowing through the clamping capacitor in opposite directions in the two conduction combinations. Therefore the voltage of the clamping capacitor can be balanced by controlling the two conduction combinations. Similarly, when outputting a negative voltage, the voltage of the clamping capacitor can be balanced by controlling other two conduction combinations. Therefore, a balance of power capacitor voltage can be achieved at full power and full modulation without adding an extra hardware circuit.